diff mbox series

[v2,08/46] KVM: SVM: Drop explicit MMU reset at RESET/INIT

Message ID	20210713163324.627647-9-seanjc@google.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@kernel.org> Reply-To: Sean Christopherson <seanjc@google.com> Date: Tue, 13 Jul 2021 09:32:46 -0700 In-Reply-To: <20210713163324.627647-1-seanjc@google.com> Message-Id: <20210713163324.627647-9-seanjc@google.com> Mime-Version: 1.0 References: <20210713163324.627647-1-seanjc@google.com> Subject: [PATCH v2 08/46] KVM: SVM: Drop explicit MMU reset at RESET/INIT From: Sean Christopherson <seanjc@google.com> To: Paolo Bonzini <pbonzini@redhat.com> Cc: Sean Christopherson <seanjc@google.com>, Vitaly Kuznetsov <vkuznets@redhat.com>, Wanpeng Li <wanpengli@tencent.com>, Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Reiji Watanabe <reijiw@google.com> Content-Type: text/plain; charset="UTF-8" Precedence: bulk
Series	KVM: x86: vCPU RESET/INIT fixes and consolidation \| expand [v2,00/46] KVM: x86: vCPU RESET/INIT fixes and consolidation [v2,01/46] KVM: x86: Flush the guest's TLB on INIT [v2,02/46] KVM: nVMX: Set LDTR to its architecturally defined value on nested VM-Exit [v2,03/46] KVM: SVM: Zero out GDTR.base and IDTR.base on INIT [v2,04/46] KVM: VMX: Set EDX at INIT with CPUID.0x1, Family-Model-Stepping [v2,05/46] KVM: SVM: Require exact CPUID.0x1 match when stuffing EDX at INIT [v2,06/46] KVM: SVM: Fall back to KVM's hardcoded value for EDX at RESET/INIT [v2,07/46] KVM: VMX: Remove explicit MMU reset in enter_rmode() [v2,08/46] KVM: SVM: Drop explicit MMU reset at RESET/INIT [v2,09/46] KVM: SVM: Drop a redundant init_vmcb() from svm_create_vcpu() [v2,10/46] KVM: VMX: Move init_vmcs() invocation to vmx_vcpu_reset() [v2,11/46] KVM: x86: WARN if the APIC map is dirty without an in-kernel local APIC [v2,12/46] KVM: x86: Remove defunct BSP "update" in local APIC reset [v2,13/46] KVM: x86: Migrate the PIT only if vcpu0 is migrated, not any BSP [v2,14/46] KVM: x86: Don't force set BSP bit when local APIC is managed by userspace [v2,15/46] KVM: x86: Set BSP bit in reset BSP vCPU's APIC base by default [v2,16/46] KVM: VMX: Stuff vcpu->arch.apic_base directly at vCPU RESET [v2,17/46] KVM: x86: Open code necessary bits of kvm_lapic_set_base() at vCPU RESET [v2,18/46] KVM: x86: Consolidate APIC base RESET initialization code [v2,19/46] KVM: x86: Move EDX initialization at vCPU RESET to common code [v2,20/46] KVM: SVM: Don't bother writing vmcb->save.rip at vCPU RESET/INIT [v2,21/46] KVM: VMX: Invert handling of CR0.WP for EPT without unrestricted guest [v2,22/46] KVM: VMX: Remove direct write to vcpu->arch.cr0 during vCPU RESET/INIT [v2,23/46] KVM: VMX: Fold ept_update_paging_mode_cr0() back into vmx_set_cr0() [v2,24/46] KVM: nVMX: Do not clear CR3 load/store exiting bits if L1 wants 'em [v2,25/46] KVM: VMX: Pull GUEST_CR3 from the VMCS iff CR3 load exiting is disabled [v2,26/46] KVM: x86/mmu: Skip the permission_fault() check on MMIO if CR0.PG=0 [v2,27/46] KVM: VMX: Process CR0.PG side effects after setting CR0 assets [v2,28/46] KVM: VMX: Skip emulation required checks during pmode/rmode transitions [v2,29/46] KVM: nVMX: Don't evaluate "emulation required" on nested VM-Exit [v2,30/46] KVM: SVM: Tweak order of cr0/cr4/efer writes at RESET/INIT [v2,31/46] KVM: SVM: Drop redundant writes to vmcb->save.cr4 at RESET/INIT [v2,32/46] KVM: SVM: Stuff save->dr6 at during VMSA sync, not at RESET/INIT [v2,33/46] KVM: VMX: Skip pointless MSR bitmap update when setting EFER [v2,34/46] KVM: VMX: Refresh list of user return MSRs after setting guest CPUID [v2,35/46] KVM: VMX: Don't _explicitly_ reconfigure user return MSRs on vCPU INIT [v2,36/46] KVM: x86: Move setting of sregs during vCPU RESET/INIT to common x86 [v2,37/46] KVM: VMX: Remove obsolete MSR bitmap refresh at vCPU RESET/INIT [v2,38/46] KVM: nVMX: Remove obsolete MSR bitmap refresh at nested transitions [v2,39/46] KVM: VMX: Don't redo x2APIC MSR bitmaps when userspace filter is changed [v2,40/46] KVM: VMX: Remove unnecessary initialization of msr_bitmap_mode [v2,41/46] KVM: VMX: Smush x2APIC MSR bitmap adjustments into single function [v2,42/46] KVM: VMX: Remove redundant write to set vCPU as active at RESET/INIT [v2,43/46] KVM: VMX: Move RESET-only VMWRITE sequences to init_vmcs() [v2,44/46] KVM: SVM: Emulate #INIT in response to triple fault shutdown [v2,45/46] KVM: SVM: Drop redundant clearing of vcpu->arch.hflags at INIT/RESET [v2,46/46] KVM: x86: Preserve guest's CR0.CD/NW on INIT

Commit Message

Sean Christopherson July 13, 2021, 4:32 p.m. UTC

Drop an explicit MMU reset in SVM's vCPU RESET/INIT flow now that the
common x86 path correctly handles conditional MMU resets, e.g. if INIT
arrives while the vCPU is in 64-bit mode.

This reverts commit ebae871a509d ("kvm: svm: reset mmu on VCPU reset").

Reviewed-by: Reiji Watanabe <reijiw@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 arch/x86/kvm/svm/svm.c | 1 -
 1 file changed, 1 deletion(-)

diff mbox series

Patch

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 7da214660c64..44248548be7d 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -1274,7 +1274,6 @@  static void init_vmcb(struct kvm_vcpu *vcpu)
 	 * It also updates the guest-visible cr0 value.
 	 */
 	svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
-	kvm_mmu_reset_context(vcpu);
 
 	save->cr4 = X86_CR4_PAE;