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(163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id l35sm1840348wms.40.2021.09.02.09.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:16:52 -0700 (PDT) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 11/30] target/cris: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:24 +0200 Message-Id: <20210902161543.417092-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/cris/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c2e7483f5bd..d6e486746be 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -35,10 +35,12 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc = value; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool cris_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ static void cris_cpu_reset(DeviceState *dev) { @@ -208,6 +210,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = { .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = cris_cpu_has_work, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -294,7 +297,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; - cc->has_work = cris_cpu_has_work; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register;