From patchwork Tue Sep 14 22:31:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raghavendra Rao Ananta X-Patchwork-Id: 12494999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFA29C433F5 for ; Tue, 14 Sep 2021 22:31:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9054461209 for ; Tue, 14 Sep 2021 22:31:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235721AbhINWcs (ORCPT ); Tue, 14 Sep 2021 18:32:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235637AbhINWcn (ORCPT ); Tue, 14 Sep 2021 18:32:43 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93216C061762 for ; Tue, 14 Sep 2021 15:31:25 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id g15-20020a63564f000000b00261998c1b70so376306pgm.5 for ; Tue, 14 Sep 2021 15:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=S2j8r1BCKqhVhJ+8bR7t/dA2J/PIIE/Rns3zAg7zZww=; b=SF+8jytE6tsk7OdA1EjKqcwdx9BTnDEREQgH6nl2uYaQV6EsWg9JbEN1WShtL0KrTK nIJrAF8y6vYLIizVYUdOeQM3tqJNxxCw25p/g7bhvEHMt0ttYN5R5m4oqvgDEttZJYNp jGhndv6Q7RT3FSoSJyS2jvzSCkY3lH5Vb+skzup8e1pD3ppCKZhFcxdVKtRVhOp1H40U Ehg1qIXzFtqoy3sgq12X2c1wb0cLIVod97evqV5ZXRyTDhW001I2Uo5WcNl35wkl/TG4 DF42qFBq26VDenW/Kz1W7jxnPPAD53T19C1mYz8TTNRznLL5dZ+UsN77LxSTxVTbMBMQ IeXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=S2j8r1BCKqhVhJ+8bR7t/dA2J/PIIE/Rns3zAg7zZww=; b=jSvHuce3yjkwNB3LXpKe9cRKP6A9m01sHMSrTr02O9DY0mnq3dmf0ZyOURujUJt4r1 ybvjkVqVpqHpo52xo6dknNzn93GDToLXOWeH7gCrDrP9SXtjxwr/AzaMlk1WMUWDTgMm 3M4V9Fm8KIm8rMfz3OF4uHjul/qUnw1KF5mVEabaSOqWEPZJBM/W2mS0+uA6xpKiAhnq FfGO6nfHAwcHYjlO2AkxD8IR4J4G5gNR6OOjDjMUZGtYuUxVqzbezy/YgGCFtXXlcUVy XzoEOxoCWSwFzk3iuYgmVIiTHQkLbsDh5WTMNJ3BJ/SkJSnR1LwDir+4kLVeymVPn8Qq mesw== X-Gm-Message-State: AOAM530VSXGG+i4XvqVcKEPZz0iufQKRzeV7P5TE/w3fgoQePvfGA7gT gDHgRxSqDPH792ep8feWzN6piGGedY7g X-Google-Smtp-Source: ABdhPJznyX0vOJEHN8tDK0ykFp8Ok1BU6n72Ike+NrTzqOrtDgUxbHGRXF1d5AyiWweWcLPS52UxS5UGLckH X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a17:90b:fd7:: with SMTP id gd23mr57225pjb.1.1631658684598; Tue, 14 Sep 2021 15:31:24 -0700 (PDT) Date: Tue, 14 Sep 2021 22:31:00 +0000 In-Reply-To: <20210914223114.435273-1-rananta@google.com> Message-Id: <20210914223114.435273-2-rananta@google.com> Mime-Version: 1.0 References: <20210914223114.435273-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.309.g3052b89438-goog Subject: [PATCH v7 01/15] KVM: arm64: selftests: Add MMIO readl/writel support From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Define the readl() and writel() functions for the guests to access (4-byte) the MMIO region. The routines, and their dependents, are inspired from the kernel's arch/arm64/include/asm/io.h and arch/arm64/include/asm/barrier.h. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Oliver Upton Reviewed-by: Andrew Jones --- .../selftests/kvm/include/aarch64/processor.h | 46 ++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index c0273aefa63d..96578bd46a85 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -9,6 +9,7 @@ #include "kvm_util.h" #include +#include #define ARM64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ @@ -130,6 +131,49 @@ void vm_install_sync_handler(struct kvm_vm *vm, val; \ }) -#define isb() asm volatile("isb" : : : "memory") +#define isb() asm volatile("isb" : : : "memory") +#define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define dmb(opt) asm volatile("dmb " #opt : : : "memory") + +#define dma_wmb() dmb(oshst) +#define __iowmb() dma_wmb() + +#define dma_rmb() dmb(oshld) + +#define __iormb(v) \ +({ \ + unsigned long tmp; \ + \ + dma_rmb(); \ + \ + /* \ + * Courtesy of arch/arm64/include/asm/io.h: \ + * Create a dummy control dependency from the IO read to any \ + * later instructions. This ensures that a subsequent call \ + * to udelay() will be ordered due to the ISB in __delay(). \ + */ \ + asm volatile("eor %0, %1, %1\n" \ + "cbnz %0, ." \ + : "=r" (tmp) : "r" ((unsigned long)(v)) \ + : "memory"); \ +}) + +static __always_inline void __raw_writel(u32 val, volatile void *addr) +{ + asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); +} + +static __always_inline u32 __raw_readl(const volatile void *addr) +{ + u32 val; + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));}) +#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) #endif /* SELFTEST_KVM_PROCESSOR_H */