diff mbox series

[kvm-unit-tests,33/39] nVMX: Add helpers to check for 4/5-level EPT support

Message ID 20211125012857.508243-34-seanjc@google.com (mailing list archive)
State New, archived
Headers show
Series x86/access: nVMX: Big overhaul | expand

Commit Message

Sean Christopherson Nov. 25, 2021, 1:28 a.m. UTC 
Add helpers to check for 4-level and 5-level EPT support.  Yet another
baby step toward removing unnecessary RDMSRs...

Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 x86/vmx.h       | 10 ++++++++++
 x86/vmx_tests.c |  4 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/x86/vmx.h b/x86/vmx.h
index 9f91602..e6126e4 100644
--- a/x86/vmx.h
+++ b/x86/vmx.h
@@ -815,6 +815,16 @@  static inline bool ept_ad_bits_supported(void)
 	return ept_vpid.val & EPT_CAP_AD_FLAG;
 }
 
+static inline bool is_4_level_ept_supported(void)
+{
+	return ept_vpid.val & EPT_CAP_PWL4;
+}
+
+static inline bool is_5_level_ept_supported(void)
+{
+	return ept_vpid.val & EPT_CAP_PWL5;
+}
+
 static inline bool is_invept_type_supported(u64 type)
 {
 	if (type < INVEPT_SINGLE || type > INVEPT_GLOBAL)
diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index 116ae66..2bfc794 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -4735,7 +4735,7 @@  static void test_ept_eptp(void)
 		wr_bk = true;
 
 	/* Support for 4-level EPT is mandatory. */
-	report(msr & EPT_CAP_PWL4, "4-level EPT support check");
+	report(is_4_level_ept_supported(), "4-level EPT support check");
 
 	primary |= CPU_SECONDARY;
 	vmcs_write(CPU_EXEC_CTRL0, primary);
@@ -4784,7 +4784,7 @@  static void test_ept_eptp(void)
 	for (i = 0; i < 8; i++) {
 		eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) |
 		    (i << EPTP_PG_WALK_LEN_SHIFT);
-		if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5)))
+		if (i == 3 || (i == 4 && is_5_level_ept_supported()))
 			ctrl = true;
 		else
 			ctrl = false;