| Message ID | 20211201092619.60298-1-zhenzhong.duan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [kvm-unit-tests] x86: Remove invalid clwb test code | expand |
+ Paolo explicitly On 12/1/2021 5:26 PM, Zhenzhong Duan wrote: > When X86_FEATURE_WAITPKG(CPUID.7.0:ECX.WAITPKG[bit 5]) supported, > ".byte 0x66, 0x0f, 0xae, 0xf0" sequence no longer represents clwb > instruction with invalid operand but tpause instruction with %eax > as input register. > > Execute tpause with invalid input triggers #GP with below customed > qemu command line: > > qemu -kernel x86/memory.flat -overcommit cpu-pm=on ... > > Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> > --- > x86/memory.c | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/x86/memory.c b/x86/memory.c > index 8f61020..351e7c0 100644 > --- a/x86/memory.c > +++ b/x86/memory.c > @@ -67,13 +67,6 @@ int main(int ac, char **av) > asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target)); > report(ud == expected, "clwb (%s)", expected ? "ABSENT" : "present"); > > - ud = 0; > - /* clwb requires a memory operand, the following is NOT a valid > - * CLWB instruction (modrm == 0xF0). > - */ > - asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0"); > - report(ud, "invalid clwb"); > - > expected = !this_cpu_has(X86_FEATURE_PCOMMIT); /* PCOMMIT */ > ud = 0; > /* pcommit: */ >
On 12/3/21 06:54, Xiaoyao Li wrote: > + Paolo explicitly > > On 12/1/2021 5:26 PM, Zhenzhong Duan wrote: >> When X86_FEATURE_WAITPKG(CPUID.7.0:ECX.WAITPKG[bit 5]) supported, >> ".byte 0x66, 0x0f, 0xae, 0xf0" sequence no longer represents clwb >> instruction with invalid operand but tpause instruction with %eax >> as input register. >> >> Execute tpause with invalid input triggers #GP with below customed >> qemu command line: >> >> qemu -kernel x86/memory.flat -overcommit cpu-pm=on ... >> >> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> >> --- >> x86/memory.c | 7 ------- >> 1 file changed, 7 deletions(-) >> >> diff --git a/x86/memory.c b/x86/memory.c >> index 8f61020..351e7c0 100644 >> --- a/x86/memory.c >> +++ b/x86/memory.c >> @@ -67,13 +67,6 @@ int main(int ac, char **av) >> asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target)); >> report(ud == expected, "clwb (%s)", expected ? "ABSENT" : >> "present"); >> - ud = 0; >> - /* clwb requires a memory operand, the following is NOT a valid >> - * CLWB instruction (modrm == 0xF0). >> - */ >> - asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0"); >> - report(ud, "invalid clwb"); >> - >> expected = !this_cpu_has(X86_FEATURE_PCOMMIT); /* PCOMMIT */ >> ud = 0; >> /* pcommit: */ >> > Applied, thanks. Paolo
diff --git a/x86/memory.c b/x86/memory.c index 8f61020..351e7c0 100644 --- a/x86/memory.c +++ b/x86/memory.c @@ -67,13 +67,6 @@ int main(int ac, char **av) asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target)); report(ud == expected, "clwb (%s)", expected ? "ABSENT" : "present"); - ud = 0; - /* clwb requires a memory operand, the following is NOT a valid - * CLWB instruction (modrm == 0xF0). - */ - asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0"); - report(ud, "invalid clwb"); - expected = !this_cpu_has(X86_FEATURE_PCOMMIT); /* PCOMMIT */ ud = 0; /* pcommit: */
When X86_FEATURE_WAITPKG(CPUID.7.0:ECX.WAITPKG[bit 5]) supported, ".byte 0x66, 0x0f, 0xae, 0xf0" sequence no longer represents clwb instruction with invalid operand but tpause instruction with %eax as input register. Execute tpause with invalid input triggers #GP with below customed qemu command line: qemu -kernel x86/memory.flat -overcommit cpu-pm=on ... Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> --- x86/memory.c | 7 ------- 1 file changed, 7 deletions(-)