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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Thu, 2 Dec 2021 23:59:18 +0000 Received: from sos-ubuntu2004-quartz01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 2 Dec 2021 17:59:15 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 2/3] x86/apic: Add helper function to get maximum physical APIC ID Date: Thu, 2 Dec 2021 17:58:24 -0600 Message-ID: <20211202235825.12562-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> References: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 20121b59-ff1e-4c27-bcb9-08d9b5efc0bd X-MS-TrafficTypeDiagnostic: BN8PR12MB2897: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1148; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 23:59:18.3465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20121b59-ff1e-4c27-bcb9-08d9b5efc0bd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2897 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Export the max_physical_apicid via a helper function since this information is required by AMD SVM AVIC support. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/apic.h | 1 + arch/x86/kernel/apic/apic.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 48067af94678..77d9cb2a7e28 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -435,6 +435,7 @@ static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} #endif /* CONFIG_X86_LOCAL_APIC */ extern void apic_ack_irq(struct irq_data *data); +extern u32 apic_get_max_phys_apicid(void); static inline void ack_APIC_irq(void) { diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index b70344bf6600..47653d8c05f2 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2361,6 +2361,12 @@ bool apic_id_is_primary_thread(unsigned int apicid) } #endif +u32 apic_get_max_phys_apicid(void) +{ + return max_physical_apicid; +} +EXPORT_SYMBOL_GPL(apic_get_max_phys_apicid); + /* * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids * and cpuid_to_apicid[] synchronized.