Message ID | 20211210100732.1080-5-jiangyifei@huawei.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add riscv kvm accel support | expand |
On Fri, Dec 10, 2021 at 3:37 PM Yifei Jiang <jiangyifei@huawei.com> wrote: > > Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Mingwang Li <limingwang@huawei.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Looks good to me. Reviewed-by: Anup Patel <anup.patel@wdc.com> Regards, Anup > --- > target/riscv/kvm.c | 112 ++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 111 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index ccf3753048..6d4df0ef6d 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -55,13 +55,123 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx > return id; > } > > +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ > + KVM_REG_RISCV_CORE_REG(name)) > + > +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ > + KVM_REG_RISCV_CSR_REG(name)) > + > +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) > + > +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) > + > +#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ > + do { \ > + int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ > + if (ret) { \ > + return ret; \ > + } \ > + } while(0) > + > +static int kvm_riscv_get_regs_core(CPUState *cs) > +{ > + int ret = 0; > + int i; > + target_ulong reg; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); > + if (ret) { > + return ret; > + } > + env->pc = reg; > + > + for (i = 1; i < 32; i++) { > + uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); > + ret = kvm_get_one_reg(cs, id, ®); > + if (ret) { > + return ret; > + } > + env->gpr[i] = reg; > + } > + > + return ret; > +} > + > +static int kvm_riscv_get_regs_csr(CPUState *cs) > +{ > + int ret = 0; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); > + KVM_RISCV_GET_CSR(cs, env, sie, env->mie); > + KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); > + KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); > + KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); > + KVM_RISCV_GET_CSR(cs, env, scause, env->scause); > + KVM_RISCV_GET_CSR(cs, env, stval, env->stval); > + KVM_RISCV_GET_CSR(cs, env, sip, env->mip); > + KVM_RISCV_GET_CSR(cs, env, satp, env->satp); > + return ret; > +} > + > +static int kvm_riscv_get_regs_fp(CPUState *cs) > +{ > + int ret = 0; > + int i; > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + > + if (riscv_has_ext(env, RVD)) { > + uint64_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + if (riscv_has_ext(env, RVF)) { > + uint32_t reg; > + for (i = 0; i < 32; i++) { > + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); > + if (ret) { > + return ret; > + } > + env->fpr[i] = reg; > + } > + return ret; > + } > + > + return ret; > +} > + > const KVMCapabilityInfo kvm_arch_required_capabilities[] = { > KVM_CAP_LAST_INFO > }; > > int kvm_arch_get_registers(CPUState *cs) > { > - return 0; > + int ret = 0; > + > + ret = kvm_riscv_get_regs_core(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_csr(cs); > + if (ret) { > + return ret; > + } > + > + ret = kvm_riscv_get_regs_fp(cs); > + if (ret) { > + return ret; > + } > + > + return ret; > } > > int kvm_arch_put_registers(CPUState *cs, int level) > -- > 2.19.1 >
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index ccf3753048..6d4df0ef6d 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -55,13 +55,123 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx return id; } +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) + +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name)) + +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx) + +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) + +#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ + do { \ + int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + if (ret) { \ + return ret; \ + } \ + } while(0) + +static int kvm_riscv_get_regs_core(CPUState *cs) +{ + int ret = 0; + int i; + target_ulong reg; + CPURISCVState *env = &RISCV_CPU(cs)->env; + + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + if (ret) { + return ret; + } + env->pc = reg; + + for (i = 1; i < 32; i++) { + uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); + ret = kvm_get_one_reg(cs, id, ®); + if (ret) { + return ret; + } + env->gpr[i] = reg; + } + + return ret; +} + +static int kvm_riscv_get_regs_csr(CPUState *cs) +{ + int ret = 0; + CPURISCVState *env = &RISCV_CPU(cs)->env; + + KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); + KVM_RISCV_GET_CSR(cs, env, sie, env->mie); + KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); + KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); + KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); + KVM_RISCV_GET_CSR(cs, env, scause, env->scause); + KVM_RISCV_GET_CSR(cs, env, stval, env->stval); + KVM_RISCV_GET_CSR(cs, env, sip, env->mip); + KVM_RISCV_GET_CSR(cs, env, satp, env->satp); + return ret; +} + +static int kvm_riscv_get_regs_fp(CPUState *cs) +{ + int ret = 0; + int i; + CPURISCVState *env = &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i = 0; i < 32; i++) { + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); + if (ret) { + return ret; + } + env->fpr[i] = reg; + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i = 0; i < 32; i++) { + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®); + if (ret) { + return ret; + } + env->fpr[i] = reg; + } + return ret; + } + + return ret; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; int kvm_arch_get_registers(CPUState *cs) { - return 0; + int ret = 0; + + ret = kvm_riscv_get_regs_core(cs); + if (ret) { + return ret; + } + + ret = kvm_riscv_get_regs_csr(cs); + if (ret) { + return ret; + } + + ret = kvm_riscv_get_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } int kvm_arch_put_registers(CPUState *cs, int level)