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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Dec 2021 06:22:53.5523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3943b854-7810-493f-d1fa-08d9ca93a58f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3980 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add coverage for BP exception handling in L2 when only L2 BP exception handler is registered BP exception is generated using int3 instruction and it is handled by L2 BP exception handler. Signed-off-by: Manali Shukla --- x86/svm_tests.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index 681272c..ed67ae1 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -2962,6 +2962,26 @@ static bool vgif_check(struct svm_test *test) return get_test_stage(test) == 3; } +static int bp_test_counter; + +static void guest_test_bp_handler(struct ex_regs *r) +{ + bp_test_counter++; +} + +static void svm_bp_test_guest(struct svm_test *test) +{ + asm volatile("int3"); +} + +static void svm_int3_test(void) +{ + handle_exception(BP_VECTOR, guest_test_bp_handler); + test_set_guest(svm_bp_test_guest); + report(svm_vmrun() == SVM_EXIT_VMMCALL && bp_test_counter == 1, + "#BP is handled in L2 exception handler"); +} + static int nm_test_counter; static void guest_test_nm_handler(struct ex_regs *r) @@ -3127,5 +3147,6 @@ struct svm_test svm_tests[] = { TEST(svm_vmload_vmsave), TEST(svm_test_singlestep), TEST(svm_nm_test), + TEST(svm_int3_test), { NULL, NULL, NULL, NULL, NULL, NULL, NULL } };