[v5,13/13] target/riscv: enable riscv kvm accel

Message ID	20220112081329.1835-14-jiangyifei@huawei.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@kernel.org> From: Yifei Jiang <jiangyifei@huawei.com> To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org> CC: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>, <libvir-list@redhat.com>, <anup@brainfault.org>, <palmer@dabbelt.com>, <Alistair.Francis@wdc.com>, <bin.meng@windriver.com>, <fanliang@huawei.com>, <wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>, <wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>, Mingwang Li <limingwang@huawei.com> Subject: [PATCH v5 13/13] target/riscv: enable riscv kvm accel Date: Wed, 12 Jan 2022 16:13:29 +0800 Message-ID: <20220112081329.1835-14-jiangyifei@huawei.com> In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com> References: <20220112081329.1835-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain Precedence: bulk
Series	Add riscv kvm accel support \| expand [v5,00/13] Add riscv kvm accel support [v5,01/13] update-linux-headers: Add asm-riscv/kvm.h [v5,02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface [v5,03/13] target/riscv: Implement function kvm_arch_init_vcpu [v5,04/13] target/riscv: Implement kvm_arch_get_registers [v5,05/13] target/riscv: Implement kvm_arch_put_registers [v5,06/13] target/riscv: Support start kernel directly by KVM [v5,07/13] target/riscv: Support setting external interrupt by KVM [v5,08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit [v5,09/13] target/riscv: Add host cpu type [v5,10/13] target/riscv: Add kvm_riscv_get/put_regs_timer [v5,11/13] target/riscv: Implement virtual time adjusting with vm state changing [v5,12/13] target/riscv: Support virtual time context synchronization [v5,13/13] target/riscv: enable riscv kvm accel

Message ID

20220112081329.1835-14-jiangyifei@huawei.com (mailing list archive)

State

New, archived

Headers

From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
CC: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
        <libvir-list@redhat.com>, <anup@brainfault.org>,
        <palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
        <bin.meng@windriver.com>, <fanliang@huawei.com>,
        <wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
        <wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
        Mingwang Li <limingwang@huawei.com>
Subject: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
Date: Wed, 12 Jan 2022 16:13:29 +0800
Message-ID: <20220112081329.1835-14-jiangyifei@huawei.com>
In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com>
References: <20220112081329.1835-1-jiangyifei@huawei.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Content-Type: text/plain
Precedence: bulk

Series

Add riscv kvm accel support | expand

Add riscv kvm support in meson.build file. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> --- meson.build | 2 ++ 1 file changed, 2 insertions(+)

Comments

Alistair Francis Jan. 13, 2022, 4:30 a.m. UTC | #1

On Wed, Jan 12, 2022 at 6:25 PM Yifei Jiang via <qemu-devel@nongnu.org> wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  meson.build | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/meson.build b/meson.build
> index c1b1db1e28..06a5476254 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
>    kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
>  elif cpu in ['mips', 'mips64']
>    kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
> +elif cpu in ['riscv']
> +  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
>  else
>    kvm_targets = []
>  endif
> --
> 2.19.1
>
>

Anup Patel Jan. 13, 2022, 4:41 a.m. UTC | #2

On Wed, Jan 12, 2022 at 1:44 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  meson.build | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/meson.build b/meson.build
> index c1b1db1e28..06a5476254 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
>    kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
>  elif cpu in ['mips', 'mips64']
>    kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
> +elif cpu in ['riscv']
> +  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
>  else
>    kvm_targets = []
>  endif
> --
> 2.19.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv

diff --git a/meson.build b/meson.build
index c1b1db1e28..06a5476254 100644
--- a/meson.build
+++ b/meson.build
@@ -90,6 +90,8 @@  elif cpu in ['ppc', 'ppc64']
   kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
 elif cpu in ['mips', 'mips64']
   kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
+elif cpu in ['riscv']
+  kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
 else
   kvm_targets = []
 endif

[v5,13/13] target/riscv: enable riscv kvm accel

Commit Message

Comments

Patch