@@ -4,7 +4,6 @@
int main(void)
{
u64 t1, t2, t3, t4, t5;
- u64 est_delta_time;
if (this_cpu_has(X86_FEATURE_TSC_ADJUST)) { // MSR_IA32_TSC_ADJUST Feature is enabled?
report(rdmsr(MSR_IA32_TSC_ADJUST) == 0x0,
@@ -26,12 +25,9 @@ int main(void)
wrtsc(t4);
t2 = rdtsc();
t5 = rdmsr(MSR_IA32_TSC_ADJUST);
- // est of time between reading tsc and writing tsc,
- // (based on MSR_IA32_TSC_ADJUST msr value) should be small
- est_delta_time = t4 - t5 - t1;
- // arbitray 2x latency (wrtsc->rdtsc) threshold
- report(est_delta_time <= (2 * (t2 - t4)),
- "MSR_IA32_TSC_ADJUST msr adjustment on tsc write");
+ report(t1 <= t4 - t5,
+ "Internal TSC advances across write to IA32_TSC");
+ report(t2 >= t4, "IA32_TSC advances after write to IA32_TSC");
}
else {
report_pass("MSR_IA32_TSC_ADJUST feature not enabled");
The subtest labeled, "MSR_IA32_TSC_ADJUST msr adjustment on tsc write," sometimes fails. The behavior tested is neither architected nor guaranteed. Running under qemu/kvm, the 'est_delta_time' has been observed to be as much as an order of magnitude greater than the expression that is supposed to be its upper bound. Remove the flaky subtest, and replace it with some invariants that actually are architecturally guaranteed (as long as IA32_TSC doesn't wrap around). Fixes: 5fecf5d8cad1 ("Added tests for ia32_tsc_adjust funtionality.") Cc: Will Auld <will.auld.intel@gmail.com> Signed-off-by: Jim Mattson <jmattson@google.com> --- x86/tsc_adjust.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-)