| Message ID | 20220128121912.509006-32-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: arm64: ARMv8.3/8.4 Nested Virtualization support | expand |
Hi Marc, On Fri, Jan 28, 2022 at 12:18:39PM +0000, Marc Zyngier wrote: > From: Christoffer Dall <christoffer.dall@linaro.org> > > So far we were flushing almost the entire universe whenever a VM would > load/unload the SCTLR_EL1 and the two versions of that register had > different MMU enabled settings. This turned out to be so slow that it > prevented forward progress for a nested VM, because a scheduler timer > tick interrupt would always be pending when we reached the nested VM. > > To avoid this problem, we consider the SCTLR_EL2 when evaluating if > caches are on or off when entering virtual EL2 (because this is the > value that we end up shadowing onto the hardware EL1 register). > > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> > Signed-off-by: Jintack Lim <jintack.lim@linaro.org> > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/include/asm/kvm_mmu.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h > index 81839e9a8a24..1b314b2a69bc 100644 > --- a/arch/arm64/include/asm/kvm_mmu.h > +++ b/arch/arm64/include/asm/kvm_mmu.h > @@ -115,6 +115,7 @@ alternative_cb_end > #include <asm/cache.h> > #include <asm/cacheflush.h> > #include <asm/mmu_context.h> > +#include <asm/kvm_emulate.h> > > void kvm_update_va_mask(struct alt_instr *alt, > __le32 *origptr, __le32 *updptr, int nr_inst); > @@ -187,7 +188,10 @@ struct kvm; > > static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) > { > - return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; > + if (vcpu_is_el2(vcpu)) > + return (__vcpu_sys_reg(vcpu, SCTLR_EL2) & 0b101) == 0b101; > + else > + return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; Might be more readable if instead of 0b101 KVM would use defines, something like: static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) { - return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; + u64 cache_bits = SCTLR_ELx_M | SCTLR_ELx_C; + + if (vcpu_is_el2(vcpu)) + return (__vcpu_sys_reg(vcpu, SCTLR_EL2) & cache_bits) == cache_bits; + else + return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & cache_bits) == cache_bits; } Regardless, it is correct to use vcpu_read_sys_reg() for the SCTLR_EL1 case, as the most recent register value could be on the CPU in the VHE case, instead of being in memory, like it's always the case with the SCTLR_EL2 register: Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com> Thanks, Alex > } > > static inline void __clean_dcache_guest_page(void *va, size_t size) > -- > 2.30.2 >
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 81839e9a8a24..1b314b2a69bc 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -115,6 +115,7 @@ alternative_cb_end #include <asm/cache.h> #include <asm/cacheflush.h> #include <asm/mmu_context.h> +#include <asm/kvm_emulate.h> void kvm_update_va_mask(struct alt_instr *alt, __le32 *origptr, __le32 *updptr, int nr_inst); @@ -187,7 +188,10 @@ struct kvm; static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) { - return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; + if (vcpu_is_el2(vcpu)) + return (__vcpu_sys_reg(vcpu, SCTLR_EL2) & 0b101) == 0b101; + else + return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; } static inline void __clean_dcache_guest_page(void *va, size_t size)