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Date: Tue, 1 Feb 2022 22:11:10 -0600 Message-ID: <20220202041112.273017-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220202041112.273017-1-suravee.suthikulpanit@amd.com> References: <20220202041112.273017-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d38a0e75-6bb0-45f6-05ba-08d9e6025f56 X-MS-TrafficTypeDiagnostic: DM6PR12MB3196:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:120; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GRYW76rGfG8ZDC0AKw0ROEBUueeDPZLXmpS/zD2HY3Dd4YFFgrXnCkylUCLn+RlfXem5CZTtFV4fom6Q1sxMY1JuBSpYzQRfwPhvDtANH23CRbA+tSbz94/ncgnbSgaMAfjZ93b6Cqi4Jbz4K5edQZankQl2q+PtxnwbAmaIeVkeUpuifg2cn1WStLb4tRlwwZuPBItGjy18BjO3SCZ6dVo4JkXZyzmQb5Lvd6k3pu0tpTPmb5uPqIkFIllk964e7naUeq0j87cFm/HbJ6RPWDkiz0sCpFYzXUPaF1eyVhMuc88caF6t2tsZRmfIPA65D70SS1/RbqW+Pc1nDX0HtJveVW48sGRQc+cu2Dsufd5Yh11tWILtWCyTU00Azpk6TCU6aT89NNk5f5oNFxv4UFweqKd52+GVf4xsrc6lOFX0BM1+IH5XL2BMf6IN+SH0T4ZRfv0NH6VkixvBqvLSrAibE2UXykE6l7piIqqBY580llu7n+qd3Ev+MPFW+zqcY+oAIz0j2AzLJo1iJHRXvgwdUU+QXG57XHZ8OQfXds5gpbFWapSDNm/hAPpBgw1AkiY5k+9dRwONEzVXxONPvCznp3nB4Xv5xEAcuHL3vDH0QUNbfloUbjFia974U03chXCRtSR6wRmjsqnK8SgqP3F5IKBZtUiuwkN3tREQF59VBbOpGbMny9fin+5bC7NZl+8YpctArAg2lQb2kFG6JxUGjSR+RYrsBbdflhr4sNtH7STeGAiLqTCrCevgYvmtUwnbGiy50glw5zGtletDYA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(82310400004)(2906002)(54906003)(7696005)(6666004)(110136005)(36756003)(7416002)(508600001)(8676002)(8936002)(316002)(44832011)(70586007)(4326008)(70206006)(5660300002)(47076005)(16526019)(83380400001)(81166007)(86362001)(356005)(1076003)(26005)(186003)(336012)(426003)(2616005)(36860700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 04:13:31.2338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d38a0e75-6bb0-45f6-05ba-08d9e6025f56 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3196 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The kvm_x86_ops.vcpu_(un)blocking are needed by AVIC only. Therefore, set the ops only when AVIC is enabled. Also, refactor AVIC hardware setup logic into helper function To prepare for upcoming AVIC changes. Suggested-by: Sean Christopherson Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm/avic.c | 17 +++++++++++++++-- arch/x86/kvm/svm/svm.c | 10 ++-------- arch/x86/kvm/svm/svm.h | 3 +-- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 90364d02f22a..f5c6cab42d74 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1027,7 +1027,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) WRITE_ONCE(*(svm->avic_physical_id_cache), entry); } -void avic_vcpu_blocking(struct kvm_vcpu *vcpu) +static void avic_vcpu_blocking(struct kvm_vcpu *vcpu) { if (!kvm_vcpu_apicv_active(vcpu)) return; @@ -1052,7 +1052,7 @@ void avic_vcpu_blocking(struct kvm_vcpu *vcpu) preempt_enable(); } -void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) +static void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) { int cpu; @@ -1066,3 +1066,16 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) put_cpu(); } + +bool avic_hardware_setup(struct kvm_x86_ops *x86_ops) +{ + if (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC)) + return false; + + x86_ops->vcpu_blocking = avic_vcpu_blocking, + x86_ops->vcpu_unblocking = avic_vcpu_unblocking, + + pr_info("AVIC enabled\n"); + amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); + return true; +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 2c99b18d76c0..459edd2a1359 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4391,8 +4391,6 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .prepare_guest_switch = svm_prepare_guest_switch, .vcpu_load = svm_vcpu_load, .vcpu_put = svm_vcpu_put, - .vcpu_blocking = avic_vcpu_blocking, - .vcpu_unblocking = avic_vcpu_unblocking, .update_exception_bitmap = svm_update_exception_bitmap, .get_msr_feature = svm_get_msr_feature, @@ -4676,13 +4674,9 @@ static __init int svm_hardware_setup(void) nrips = false; } - enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC); + enable_apicv = avic = avic && avic_hardware_setup(&svm_x86_ops); - if (enable_apicv) { - pr_info("AVIC enabled\n"); - - amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); - } else { + if (!enable_apicv) { svm_x86_ops.vcpu_blocking = NULL; svm_x86_ops.vcpu_unblocking = NULL; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 47ef8f4a9358..f2507d11a31a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -572,6 +572,7 @@ extern struct kvm_x86_nested_ops svm_nested_ops; #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL +bool avic_hardware_setup(struct kvm_x86_ops *ops); int avic_ga_log_notifier(u32 ga_tag); void avic_vm_destroy(struct kvm *kvm); int avic_vm_init(struct kvm *kvm); @@ -592,8 +593,6 @@ int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set); -void avic_vcpu_blocking(struct kvm_vcpu *vcpu); -void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); /* sev.c */