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Mon, 7 Feb 2022 05:12:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT035.mail.protection.outlook.com (10.13.172.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4951.12 via Frontend Transport; Mon, 7 Feb 2022 05:12:43 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Sun, 6 Feb 2022 23:12:40 -0600 From: Manali Shukla To: CC: , , Subject: [kvm-unit-tests PATCH 1/3] x86: Add routines to set/clear PT_USER_MASK for all pages Date: Mon, 7 Feb 2022 05:12:00 +0000 Message-ID: <20220207051202.577951-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220207051202.577951-1-manali.shukla@amd.com> References: <20220207051202.577951-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 622f34d8-1ef8-40d7-1730-08d9e9f878a4 X-MS-TrafficTypeDiagnostic: MN2PR12MB4270:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2276; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2022 05:12:43.3723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 622f34d8-1ef8-40d7-1730-08d9e9f878a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4270 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add following 2 routines : 1) set_user_mask_all() - set PT_USER_MASK for all the levels of page tables 2) clear_user_mask_all - clear PT_USER_MASK for all the levels of page tables commit 916635a813e975600335c6c47250881b7a328971 (nSVM: Add test for NPT reserved bit and #NPF error code behavior) clears PT_USER_MASK for all svm testcases. Any tests that requires usermode access will fail after this commit. Usermode function needs to be called from L2 guest to generate AC exception and calling usermode function with supervisor pages generates #PF exception with error code 0004 Add solution to above mentioned problem which is to set PT_USER_MASK for all pages in the initialization of #AC exception test and clear them in uninitialization of #AC exception at last. AC exception test works fine without hampering other test cases with this solution. Signed-off-by: Manali Shukla --- lib/x86/vm.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/x86/vm.h | 3 +++ 2 files changed, 57 insertions(+) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 56be57b..f3a7ae8 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -37,6 +37,60 @@ pteval_t *install_pte(pgd_t *cr3, return &pt[offset]; } +/* + * set PT_USER_MASK bit for all levels of page tables + */ + +void set_user_mask_all(pteval_t *pt, int level) +{ + pteval_t pte, *ptep; + int i; + + if (level == PAGE_LEVEL) + pte_opt_mask |= PT_USER_MASK; + + for (i = 0; i < 512; i++) { + ptep = &pt[i]; + pte = *ptep; + + if ((pte & PT_PRESENT_MASK) && !(pte & PT_USER_MASK)) { + *ptep |= PT_USER_MASK; + + if (level == 1 || pte & PT_PAGE_SIZE_MASK) + continue; + + set_user_mask_all(phys_to_virt(pte & 0xffffffffff000ull), level - 1); + } + } +} + + +/* + * clear PT_USER_MASK bit for all levels of page tables + */ + +void clear_user_mask_all(pteval_t *pt, int level) +{ + pteval_t pte, *ptep; + int i; + + for (i = 0; i < 512; i++) { + ptep = &pt[i]; + pte = *ptep; + + if ((pte & PT_PRESENT_MASK) && (pte & PT_USER_MASK)) { + *ptep &= ~PT_USER_MASK; + + if (level == 1 || pte & PT_PAGE_SIZE_MASK) + continue; + + clear_user_mask_all(phys_to_virt(pte & 0xffffffffff000ull), level - 1); + } + } + if (level == PAGE_LEVEL) + pte_opt_mask &= ~PT_USER_MASK; +} + /* * Finds last PTE in the mapping of @virt that's at or above @lowest_level. The * returned PTE isn't necessarily present, but its parent is. diff --git a/lib/x86/vm.h b/lib/x86/vm.h index 4c6dff9..75715e5 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -38,6 +38,9 @@ pteval_t *install_large_page(pgd_t *cr3, phys_addr_t phys, void *virt); void install_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt); bool any_present_pages(pgd_t *cr3, void *virt, size_t len); +void set_user_mask_all(pteval_t *pt, int level); +void clear_user_mask_all(pteval_t *pt, int level); + static inline void *current_page_table(void) { return phys_to_virt(read_cr3());