| Message ID | 20220209084929.54331-3-adrian.hunter@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf intel-pt: Add perf event clocks to better support VM tracing | expand |
On Wed, Feb 09, 2022 at 10:49:20AM +0200, Adrian Hunter wrote: > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h > index 82858b697c05..150d2b70a41f 100644 > --- a/include/uapi/linux/perf_event.h > +++ b/include/uapi/linux/perf_event.h > @@ -290,6 +290,14 @@ enum { > PERF_TXN_ABORT_SHIFT = 32, > }; > > +/* > + * If supported, clockid value to select an architecture dependent hardware > + * clock. Note this means the unit of time is ticks not nanoseconds. > + * On x86, this is provided by the rdtsc instruction, and is not > + * paravirtualized. > + */ > +#define CLOCK_PERF_HW_CLOCK 0x10000000 This steps on the clockid_t space; are we good with that? At some point there was talk of dynamic clock ids, that would complicate things more than they are today.
On 09/02/2022 15:11, Peter Zijlstra wrote: > On Wed, Feb 09, 2022 at 10:49:20AM +0200, Adrian Hunter wrote: >> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h >> index 82858b697c05..150d2b70a41f 100644 >> --- a/include/uapi/linux/perf_event.h >> +++ b/include/uapi/linux/perf_event.h >> @@ -290,6 +290,14 @@ enum { >> PERF_TXN_ABORT_SHIFT = 32, >> }; >> >> +/* >> + * If supported, clockid value to select an architecture dependent hardware >> + * clock. Note this means the unit of time is ticks not nanoseconds. >> + * On x86, this is provided by the rdtsc instruction, and is not >> + * paravirtualized. >> + */ >> +#define CLOCK_PERF_HW_CLOCK 0x10000000 > > This steps on the clockid_t space; are we good with that? > > At some point there was talk of dynamic clock ids, that would complicate > things more than they are today. There are 16 clock IDs at the moment and perf only supports a few of them. If there were a conflict in the future, then an attribute bit would be needed to differentiate the 2 cases: standard clock IDs vs non-standard "perf" clock IDs. An alternative would be to add that attribute bit now.
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e686c5e0537b..e2ad3f9cca93 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2728,6 +2728,15 @@ void arch_perf_update_userpage(struct perf_event *event, !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); userpg->pmc_width = x86_pmu.cntval_bits; + if (event->attr.use_clockid && event->attr.clockid == CLOCK_PERF_HW_CLOCK) { + userpg->cap_user_time_zero = 1; + userpg->time_mult = 1; + userpg->time_shift = 0; + userpg->time_offset = 0; + userpg->time_zero = 0; + return; + } + if (!using_native_sched_clock() || !sched_clock_stable()) return; @@ -2980,6 +2989,11 @@ unsigned long perf_misc_flags(struct pt_regs *regs) return misc; } +u64 perf_hw_clock(void) +{ + return rdtsc_ordered(); +} + void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) { cap->version = x86_pmu.version; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 58d9e4b1fa0a..5288ea1ae2ba 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -451,6 +451,9 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) +extern u64 perf_hw_clock(void); +#define perf_hw_clock perf_hw_clock + #include <asm/stacktrace.h> /* diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 82858b697c05..150d2b70a41f 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -290,6 +290,14 @@ enum { PERF_TXN_ABORT_SHIFT = 32, }; +/* + * If supported, clockid value to select an architecture dependent hardware + * clock. Note this means the unit of time is ticks not nanoseconds. + * On x86, this is provided by the rdtsc instruction, and is not + * paravirtualized. + */ +#define CLOCK_PERF_HW_CLOCK 0x10000000 + /* * The format of the data returned by read() on a perf event fd, * as specified by attr.read_format: diff --git a/kernel/events/core.c b/kernel/events/core.c index 57249f37c37d..aab78f033711 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12035,6 +12035,13 @@ static int perf_event_set_clock(struct perf_event *event, clockid_t clk_id) event->clock = &ktime_get_clocktai_ns; break; +#ifdef perf_hw_clock + case CLOCK_PERF_HW_CLOCK: + event->clock = &perf_hw_clock; + nmi_safe = true; + break; +#endif + default: return -EINVAL; }
Currently, using Intel PT to trace a VM guest is limited to kernel space because decoding requires side band events such as MMAP and CONTEXT_SWITCH. While these events can be collected for the host, there is not a way to do that yet for a guest. One approach, would be to collect them inside the guest, but that would require being able to synchronize with host timestamps. The motivation for this patch is to provide a clock that can be used within a VM guest, and that correlates to a VM host clock. In the case of TSC, if the hypervisor leaves rdtsc alone, the TSC value will be subject only to the VMCS TSC Offset and Scaling. Adjusting for that would make it possible to inject events from a guest perf.data file, into a host perf.data file. Thus making possible the collection of VM guest side band for Intel PT decoding. There are other potential benefits of TSC as a perf event clock: - ability to work directly with TSC - ability to inject non-Intel-PT-related events from a guest Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> --- arch/x86/events/core.c | 14 ++++++++++++++ arch/x86/include/asm/perf_event.h | 3 +++ include/uapi/linux/perf_event.h | 8 ++++++++ kernel/events/core.c | 7 +++++++ 4 files changed, 32 insertions(+)