| Message ID | 20220221162243.683208-11-pbonzini@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM MMU refactoring part 2: role changes | expand |
On Mon, Feb 21, 2022, Paolo Bonzini wrote: > The ept_ad field is used during page walk to determine if the guest PTEs > have accessed and dirty bits. In the MMU role, the ad_disabled > bit represents whether the *shadow* PTEs have the bits, so it > would be incorrect to replace PT_HAVE_ACCESSED_DIRTY with just > !mmu->mmu_role.base.ad_disabled. > > However, the similar field in the CPU mode, ad_disabled, is initialized > correctly: to the opposite value of ept_ad for shadow EPT, and zero > for non-EPT guest paging modes (which always have A/D bits). It is > therefore possible to compute PT_HAVE_ACCESSED_DIRTY from the CPU mode, > like other page-format fields; it just has to be inverted to account > for the different polarity. > > Having a CPU mode that is distinct from the MMU roles in fact would even > allow to remove PT_HAVE_ACCESSED_DIRTY macro altogether, and always use > !mmu->cpu_mode.base.ad_disabled. I am not doing this because the macro > has a small effect in terms of dead code elimination: > > text data bss dec hex > 103544 16665 112 120321 1d601 # as of this patch > 103746 16665 112 120523 1d6cb # without PT_HAVE_ACCESSED_DIRTY > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- Reviewed-by: Sean Christopherson <seanjc@google.com>
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index cc268116eb3f..996cf9b14f5e 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -437,7 +437,6 @@ struct kvm_mmu { union kvm_mmu_role mmu_role; u8 root_level; u8 shadow_root_level; - u8 ept_ad; bool direct_map; struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 6e539fc2c9c7..3ffa6f2bf991 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4936,7 +4936,6 @@ void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, context->shadow_root_level = level; - context->ept_ad = accessed_dirty; context->page_fault = ept_page_fault; context->gva_to_gpa = ept_gva_to_gpa; context->sync_page = ept_sync_page; diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h index e1c2ecb4ddee..64b6f76641f0 100644 --- a/arch/x86/kvm/mmu/paging_tmpl.h +++ b/arch/x86/kvm/mmu/paging_tmpl.h @@ -64,7 +64,7 @@ #define PT_LEVEL_BITS PT64_LEVEL_BITS #define PT_GUEST_DIRTY_SHIFT 9 #define PT_GUEST_ACCESSED_SHIFT 8 - #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad) + #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_mode.base.ad_disabled) #define CMPXCHG cmpxchg64 #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL #else
The ept_ad field is used during page walk to determine if the guest PTEs have accessed and dirty bits. In the MMU role, the ad_disabled bit represents whether the *shadow* PTEs have the bits, so it would be incorrect to replace PT_HAVE_ACCESSED_DIRTY with just !mmu->mmu_role.base.ad_disabled. However, the similar field in the CPU mode, ad_disabled, is initialized correctly: to the opposite value of ept_ad for shadow EPT, and zero for non-EPT guest paging modes (which always have A/D bits). It is therefore possible to compute PT_HAVE_ACCESSED_DIRTY from the CPU mode, like other page-format fields; it just has to be inverted to account for the different polarity. Having a CPU mode that is distinct from the MMU roles in fact would even allow to remove PT_HAVE_ACCESSED_DIRTY macro altogether, and always use !mmu->cpu_mode.base.ad_disabled. I am not doing this because the macro has a small effect in terms of dead code elimination: text data bss dec hex 103544 16665 112 120321 1d601 # as of this patch 103746 16665 112 120523 1d6cb # without PT_HAVE_ACCESSED_DIRTY Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/x86/include/asm/kvm_host.h | 1 - arch/x86/kvm/mmu/mmu.c | 1 - arch/x86/kvm/mmu/paging_tmpl.h | 2 +- 3 files changed, 1 insertion(+), 3 deletions(-)