From patchwork Thu Mar 3 07:18:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Duan, Zhenzhong" X-Patchwork-Id: 12767143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB932C433F5 for ; Thu, 3 Mar 2022 07:28:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230318AbiCCH2n (ORCPT ); Thu, 3 Mar 2022 02:28:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbiCCH2c (ORCPT ); Thu, 3 Mar 2022 02:28:32 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E967E5FE9 for ; Wed, 2 Mar 2022 23:27:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646292452; x=1677828452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pGbVvnH0+tW0IVP4OvryXS4dM2QPA9H1YCBKoJmLM34=; b=fB5P5kReeOunY2KtJ7Wt4vwZnMB/nvokAUYqxCe5QFgj43XBgYUPCVKC jaLrhq1+LPv6rLfGc7e04N+olHkTy/7q8wwzsbnlqM4bCJ6GvEjf+zVR0 LnVHhBSgow42wsbmode4wH4fNGjUqfjnjShz384pjuZcyrTKz0z7S6QRL xhftsolHaEOde4B8lX87CboZtA6f+ya2dzJD/DYdX1EaLYn0UVFp9fqPS KOqmad7fOgX61RBQWJ3UDasojjVDHuIAmRYOG1lKzLSJ1bRJvpFBcwrQz y9R4SuFKZyRKLdn9ttxk+22ObDGD18FGAniMwACfq0RNCvrYJIscSTyA5 g==; X-IronPort-AV: E=McAfee;i="6200,9189,10274"; a="252427533" X-IronPort-AV: E=Sophos;i="5.90,151,1643702400"; d="scan'208";a="252427533" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 23:27:30 -0800 X-IronPort-AV: E=Sophos;i="5.90,151,1643702400"; d="scan'208";a="551631561" Received: from duan-server-s2600bt.bj.intel.com ([10.240.192.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 23:27:27 -0800 From: Zhenzhong Duan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, yu.c.zhang@intel.com, zixuanwang@google.com, marcorr@google.com, jun.nakajima@intel.com, erdemaktas@google.com Subject: [kvm-unit-tests RFC PATCH 05/17] x86 TDX: bypass wrmsr simulation on some specific MSRs Date: Thu, 3 Mar 2022 15:18:55 +0800 Message-Id: <20220303071907.650203-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303071907.650203-1-zhenzhong.duan@intel.com> References: <20220303071907.650203-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In TDX scenario, some MSRs are initialized with expected value and not expected to be changed in TD-guest. Writing to MSR_IA32_TSC, MSR_IA32_APICBASE, MSR_EFER in TD-guest triggers #VE. In #VE handler these MSR access are simulated with tdvmcall. But in current TDX host side implementation, they are bypassed and return failure. In order to let test cases touching those MSRs run smoothly, bypass writing to those MSRs in #VE handler just like writing succeed. Signed-off-by: Zhenzhong Duan Reviewed-by: Yu Zhang --- lib/x86/tdx.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/lib/x86/tdx.c b/lib/x86/tdx.c index 62e0e2842822..1fc8030c34fa 100644 --- a/lib/x86/tdx.c +++ b/lib/x86/tdx.c @@ -311,6 +311,18 @@ static bool tdx_get_ve_info(struct ve_info *ve) return true; } +static bool tdx_is_bypassed_msr(u32 index) +{ + switch (index) { + case MSR_IA32_TSC: + case MSR_IA32_APICBASE: + case MSR_EFER: + return true; + default: + return false; + } +} + static bool tdx_handle_virtualization_exception(struct ex_regs *regs, struct ve_info *ve) { @@ -338,7 +350,8 @@ static bool tdx_handle_virtualization_exception(struct ex_regs *regs, } break; case EXIT_REASON_MSR_WRITE: - ret = tdx_write_msr(regs->rcx, regs->rax, regs->rdx); + if (!tdx_is_bypassed_msr(regs->rcx)) + ret = tdx_write_msr(regs->rcx, regs->rax, regs->rdx); break; case EXIT_REASON_CPUID: ret = tdx_handle_cpuid(regs);