From patchwork Mon Mar 7 08:53:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Hunter X-Patchwork-Id: 12771379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A9F9C433F5 for ; Mon, 7 Mar 2022 08:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235443AbiCGIyv (ORCPT ); Mon, 7 Mar 2022 03:54:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236237AbiCGIyk (ORCPT ); Mon, 7 Mar 2022 03:54:40 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1068A1AF20; Mon, 7 Mar 2022 00:53:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646643224; x=1678179224; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=igIfzl614SJVVpOc/yOTouOngTlxdEUS35ptrQqkkbo=; b=diMuQybr8uaLWWhTqCE+p6W3eg0IU95bszFbqFYTX8sRauKYTly6IHlQ kPXx+kpHIe26IAP3fOwHXG2hbX3rhV4IJUMvymEsedeECh2HiH1jukYMy bkycV0ZNQQsQD33rHQpSDesT222mNSk/VQK1RcKIlPGLfAgOxtVvk3xK3 fKHuJhHNNlJ4jSn2i/4WqatuQtLhIgYuNhn+yxnhL0qyhEJ1LK4uCZcs0 zcVfIgSfuiUjk8VVWmYgOPfdrrO6wxeCRJXpabJtF2uCoOMi4SRoZ4JE2 jQ3T7/JWwYrgY/xJrXRl3JPtwDAUdRtwfyt5zDHWZkJDDStTuNYCH+ULF Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="241771854" X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="241771854" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 00:53:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,161,1643702400"; d="scan'208";a="537033567" Received: from ahunter-desktop.fi.intel.com ([10.237.72.92]) by orsmga007.jf.intel.com with ESMTP; 07 Mar 2022 00:53:38 -0800 From: Adrian Hunter To: Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, kvm@vger.kernel.org, H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan Subject: [PATCH V3 06/10] perf tools: Add new clock IDs to "perf time to TSC" test Date: Mon, 7 Mar 2022 10:53:08 +0200 Message-Id: <20220307085312.1814506-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307085312.1814506-1-adrian.hunter@intel.com> References: <20220307085312.1814506-1-adrian.hunter@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The same "Convert perf time to TSC" test can be used with new clock IDs CLOCK_PERF_HW_CLOCK and CLOCK_PERF_HW_CLOCK_NS. Signed-off-by: Adrian Hunter --- tools/perf/tests/perf-time-to-tsc.c | 42 ++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c index d12d0ad81801..62840ec98cea 100644 --- a/tools/perf/tests/perf-time-to-tsc.c +++ b/tools/perf/tests/perf-time-to-tsc.c @@ -22,6 +22,8 @@ #include "tests.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "clockid.h" +#include "perf_api_probe.h" /* * Except x86_64/i386 and Arm64, other archs don't support TSC in perf. Just @@ -47,15 +49,7 @@ } \ } -/** - * test__perf_time_to_tsc - test converting perf time to TSC. - * - * This function implements a test that checks that the conversion of perf time - * to and from TSC is consistent with the order of events. If the test passes - * %0 is returned, otherwise %-1 is returned. If TSC conversion is not - * supported then then the test passes but " (not supported)" is printed. - */ -static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int subtest __maybe_unused) +static int perf_time_to_tsc_test(bool use_clockid, s32 clockid) { struct record_opts opts = { .mmap_pages = UINT_MAX, @@ -104,6 +98,8 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su evsel->core.attr.comm = 1; evsel->core.attr.disabled = 1; evsel->core.attr.enable_on_exec = 0; + evsel->core.attr.use_clockid = use_clockid; + evsel->core.attr.clockid = clockid; /* * For hybrid "cycles:u", it creates two events. @@ -200,4 +196,32 @@ static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, int su return err; } +/** + * test__perf_time_to_tsc - test converting perf time to TSC. + * + * This function implements a test that checks that the conversion of perf time + * to and from TSC is consistent with the order of events. If the test passes + * %0 is returned, otherwise %-1 is returned. If TSC conversion is not + * supported then the test passes but " (not supported)" is printed. + */ +static int test__perf_time_to_tsc(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + int err; + + err = perf_time_to_tsc_test(false, 0); + + if (!err && perf_can_perf_clock_hw_clock()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK); + } + + if (!err && perf_can_perf_clock_hw_clock_ns()) { + pr_debug("Testing CLOCK_PERF_HW_CLOCK_NS\n"); + err = perf_time_to_tsc_test(true, CLOCK_PERF_HW_CLOCK_NS); + } + + return err; +} + DEFINE_SUITE("Convert perf time to TSC", perf_time_to_tsc);