| Message ID | 20220405230855.15376-8-suravee.suthikulpanit@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introducing AMD x2APIC Virtualization (x2AVIC) support. | expand |
On 4/6/22 6:08 AM, Suravee Suthikulpanit wrote: > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index bbdc16c4b6d7..56ad9ba05111 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -89,7 +89,7 @@ static uint64_t osvw_len = 4, osvw_status; > static DEFINE_PER_CPU(u64, current_tsc_ratio); > #define TSC_RATIO_DEFAULT 0x0100000000ULL > > -static const struct svm_direct_access_msrs { > +static struct svm_direct_access_msrs { > u32 index; /* Index of the MSR */ > bool always; /* True if intercept is initially cleared */ > } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = { > @@ -786,6 +786,33 @@ static void add_msr_offset(u32 offset) > BUG(); > } > > +static void init_direct_access_msrs(void) > +{ > + int i, j; > + > + /* Find first MSR_INVALID */ > + for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) { > + if (direct_access_msrs[i].index == MSR_INVALID) > + break; > + } > + BUG_ON(i >= MAX_DIRECT_ACCESS_MSRS); > + > + /* > + * Initialize direct_access_msrs entries to intercept X2APIC MSRs > + * (range 0x800 to 0x8ff) > + */ > + for (j = 0; j < 0x100; j++) { > + direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ? > + (APIC_BASE_MSR + j) : MSR_INVALID; I found a bug in this part, when testing on system w/o support for x2AVIC feature. The following change fixes the issue. - direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ? - (APIC_BASE_MSR + j) : MSR_INVALID; + direct_access_msrs[i + j].index = (APIC_BASE_MSR + j); I will update this in V2. Regards, Suravee
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index bbdc16c4b6d7..56ad9ba05111 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -89,7 +89,7 @@ static uint64_t osvw_len = 4, osvw_status; static DEFINE_PER_CPU(u64, current_tsc_ratio); #define TSC_RATIO_DEFAULT 0x0100000000ULL -static const struct svm_direct_access_msrs { +static struct svm_direct_access_msrs { u32 index; /* Index of the MSR */ bool always; /* True if intercept is initially cleared */ } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = { @@ -786,6 +786,33 @@ static void add_msr_offset(u32 offset) BUG(); } +static void init_direct_access_msrs(void) +{ + int i, j; + + /* Find first MSR_INVALID */ + for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) { + if (direct_access_msrs[i].index == MSR_INVALID) + break; + } + BUG_ON(i >= MAX_DIRECT_ACCESS_MSRS); + + /* + * Initialize direct_access_msrs entries to intercept X2APIC MSRs + * (range 0x800 to 0x8ff) + */ + for (j = 0; j < 0x100; j++) { + direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ? + (APIC_BASE_MSR + j) : MSR_INVALID; + direct_access_msrs[i + j].always = false; + } + BUG_ON(i + j >= MAX_DIRECT_ACCESS_MSRS); + + /* Initialize last entry */ + direct_access_msrs[i + j].index = MSR_INVALID; + direct_access_msrs[i + j].always = true; +} + static void init_msrpm_offsets(void) { int i; @@ -4765,6 +4792,7 @@ static __init int svm_hardware_setup(void) memset(iopm_va, 0xff, PAGE_SIZE * (1 << order)); iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; + init_direct_access_msrs(); init_msrpm_offsets(); supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index b53c83a44ec2..0bbbe8d6a87a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -27,8 +27,9 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 20 -#define MSRPM_OFFSETS 16 +#define MAX_DIRECT_ACCESS_MSRS (20 + 0x100) +#define MSRPM_OFFSETS 30 + extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; extern bool intercept_smi;
When enabling x2APIC virtualization (x2AVIC), the interception of x2APIC MSRs must be disabled to let the hardware virtualize guest MSR accesses. Current implementation keeps track of list of MSR interception state in the svm_direct_access_msrs array. Therefore, extends the array to include x2APIC MSRs. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> --- arch/x86/kvm/svm/svm.c | 30 +++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 5 +++-- 2 files changed, 32 insertions(+), 3 deletions(-)