| Message ID | 20220411093537.11558-10-likexu@tencent.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: x86/pmu: More refactoring to get rid of PERF_TYPE_HARDWAR | expand |
On Mon, Apr 11, 2022 at 05:35:35PM +0800, Like Xu wrote: > From: Like Xu <likexu@tencent.com> > > Currently, we have [intel|knc|p4|p6]_perfmon_event_map on the Intel > platforms and amd_[f17h]_perfmon_event_map on the AMD platforms. > > Early clumsy KVM code or other potential perf_event users may have > hard-coded these perfmon_maps (e.g., arch/x86/kvm/svm/pmu.c), so > it would not make sense to program a common hardware event based > on the generic "enum perf_hw_id" once the two tables do not match. > > Let's provide an interface for callers outside the perf subsystem to get > the counter config based on the perfmon_event_map currently in use, > and it also helps to save bytes. > > Cc: Peter Zijlstra <peterz@infradead.org> > Signed-off-by: Like Xu <likexu@tencent.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index eef816fc216d..091363bc545d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2996,3 +2996,14 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) cap->events_mask_len = x86_pmu.events_mask_len; } EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); + +u64 perf_get_hw_event_config(int hw_event) +{ + int max = x86_pmu.max_events; + + if (hw_event < max) + return x86_pmu.event_map(array_index_nospec(hw_event, max)); + + return 0; +} +EXPORT_SYMBOL_GPL(perf_get_hw_event_config); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 58d9e4b1fa0a..09ab495d738a 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -477,6 +477,7 @@ struct x86_pmu_lbr { }; extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); +extern u64 perf_get_hw_event_config(int hw_event); extern void perf_check_microcode(void); extern void perf_clear_dirty_counters(void); extern int x86_perf_rdpmc_index(struct perf_event *event); @@ -486,6 +487,11 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) memset(cap, 0, sizeof(*cap)); } +static inline u64 perf_get_hw_event_config(int hw_event) +{ + return 0; +} + static inline void perf_events_lapic_init(void) { } static inline void perf_check_microcode(void) { } #endif