From patchwork Mon Apr 11 10:19:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 12808938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4180C433F5 for ; Mon, 11 Apr 2022 10:20:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345304AbiDKKW1 (ORCPT ); Mon, 11 Apr 2022 06:22:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345286AbiDKKWW (ORCPT ); Mon, 11 Apr 2022 06:22:22 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4123642EDD; Mon, 11 Apr 2022 03:20:07 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id h23-20020a17090a051700b001c9c1dd3acbso16325350pjh.3; Mon, 11 Apr 2022 03:20:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P2aSE95nIo5Or2XH6dTQCly51gSkLA5/yjtRsQMPMDA=; b=Vf5ZiMYfyIsvV3gLJq0u31jxztPwimA5n3xItAv73lnh6cZdBirETl9pE4ctUYgb9p a8/BAYiFgFrGIJ0quMi09g2cX5oWfsWqNgPVXtBHSAOqBmaxKuAFfBVDz0sB1zboP3OG WeM+FPKC+HI5s8L+ssEZ+ys/nwuB+tzSubbMQvbgvZ77Euv7o43H26vry+z0qqVdIlP8 UReLrONoGcqd1p8CKeL6RhePpS2rd87tpAbDOOjy3rJR72xwNAQOXtPkBXx1Sas7ALVd opA5YaG5bzPLxInFbnmz2ON2Qw32N/RavscDnn9mw4z0gjsge9zk8EewuuHYMbiKA2H/ wECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P2aSE95nIo5Or2XH6dTQCly51gSkLA5/yjtRsQMPMDA=; b=mYEcJCVRzFEdNyiKQ2UFw9gvXdhLJ6qhHz8HVX4OsIH7kt+StgiPkuJZK9D5Fmw014 MdMaNbBYJo8Q3pUekEFCQwq2JQVcHtQBfmdkd5eYbmkyGjQVel0FjStGDGPhVc/dwfNj TAJKLCjes7CQoI0xfc6JmliP8wzpu4mKsRsIZESy1ZgnKvS5oDx5eSW/dxdqEhvhyoJ6 TE3iLCCDHlvxaqKX2Ei8SEgOWmD1mF0MqPSQbqgSR9ByW10eETa/upC6M6BGCgJtFvOr fn4BsXXbYc4EEOSaM4L+8oKXcLXTN6q5mqm8KXG/YR6Rinbov04YY37w7ByVgCaPv3On //JQ== X-Gm-Message-State: AOAM5336AW6ykUzZ748M00jwCx6Y3T6idDkCd2/32EFa5MwEa4Hd0M0+ zPOwDvpyUvEmpU9ndFxogfI= X-Google-Smtp-Source: ABdhPJzZ1XsjGV8UnyMgDQj3Y/ULOqCYflwIcwvCkM1fAUVce725O3IkP9hpCt1rrw/4UM1oXld9Dw== X-Received: by 2002:a17:90a:734a:b0:1ca:8240:9e48 with SMTP id j10-20020a17090a734a00b001ca82409e48mr35713842pjs.174.1649672407299; Mon, 11 Apr 2022 03:20:07 -0700 (PDT) Received: from localhost.localdomain ([203.205.141.112]) by smtp.gmail.com with ESMTPSA id h10-20020a056a00230a00b004faa0f67c3esm34012280pfh.23.2022.04.11.03.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 03:20:07 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Paolo Bonzini , Jim Mattson Cc: Peter Zijlstra , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Joerg Roedel , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH RESEND v12 05/17] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Date: Mon, 11 Apr 2022 18:19:34 +0800 Message-Id: <20220411101946.20262-6-likexu@tencent.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220411101946.20262-1-likexu@tencent.com> References: <20220411101946.20262-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The mask value of fixed counter control register should be dynamic adjusted with the number of fixed counters. This patch introduces a variable that includes the reserved bits of fixed counter control registers. This is a generic code refactoring. Co-developed-by: Luwei Kang Signed-off-by: Luwei Kang Signed-off-by: Like Xu Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 2c20f715f009..6e3eeadfe8e3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -502,6 +502,7 @@ struct kvm_pmu { unsigned nr_arch_fixed_counters; unsigned available_event_types; u64 fixed_ctr_ctrl; + u64 fixed_ctr_ctrl_mask; u64 global_ctrl; u64 global_status; u64 counter_bitmask[2]; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index e101406dafa3..2aeabb067bad 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -395,7 +395,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: if (pmu->fixed_ctr_ctrl == data) return 0; - if (!(data & 0xfffffffffffff444ull)) { + if (!(data & pmu->fixed_ctr_ctrl_mask)) { reprogram_fixed_counters(pmu, data); return 0; } @@ -483,6 +483,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) struct kvm_cpuid_entry2 *entry; union cpuid10_eax eax; union cpuid10_edx edx; + int i; pmu->nr_arch_gp_counters = 0; pmu->nr_arch_fixed_counters = 0; @@ -491,6 +492,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->version = 0; pmu->reserved_bits = 0xffffffff00200000ull; pmu->raw_event_mask = X86_RAW_EVENT_MASK; + pmu->fixed_ctr_ctrl_mask = ~0ull; entry = kvm_find_cpuid_entry(vcpu, 0xa, 0); if (!entry || !vcpu->kvm->arch.enable_pmu) @@ -527,6 +529,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) setup_fixed_pmc_eventsel(pmu); } + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) + pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4)); pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) | (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED); pmu->global_ctrl_mask = ~pmu->global_ctrl;