From patchwork Fri Apr 22 07:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 12823019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E5EC433EF for ; Fri, 22 Apr 2022 07:56:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1445312AbiDVH7C (ORCPT ); Fri, 22 Apr 2022 03:59:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1445241AbiDVH6a (ORCPT ); Fri, 22 Apr 2022 03:58:30 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6993837A95; Fri, 22 Apr 2022 00:55:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650614138; x=1682150138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QPQZgN76ZKwxqlnIKAFB0K/Rb6aYGDThbRFdYJP8k+c=; b=gZfmKymWlkdmIfxsiSzkJrvNBCO5B0CzhZB6NBNMSogab7r/gE0uXMIG jQ6mTJCP+unJ0tc+Bh6jBvgTuiXcXYdSjos8QkN3zBqFCL/B4MJEgRfHk f4HwVgHsPxn/9HpVX+BTkrhdlIpoFX7nMl7CLKOxWGARLOjI0V1H5QbCT l5/4y8XEoK5jLYOqAHso7ykQwgGsSNErXjbt0DS6H0QBY2vS0mmu+1hCo C1shTkGeRlxFp+uK1aoJ3QUpOVM4D1Ruy2heO1Uv2FewmWwQTMwJgfDKB JW1vZGiOuFNP9cKXp+71imrjWLnwmRDg94vljOkUZ06fLGuGo86C5hD35 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10324"; a="264384837" X-IronPort-AV: E=Sophos;i="5.90,281,1643702400"; d="scan'208";a="264384837" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2022 00:55:30 -0700 X-IronPort-AV: E=Sophos;i="5.90,281,1643702400"; d="scan'208";a="577741367" Received: from embargo.jf.intel.com ([10.165.9.183]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2022 00:55:30 -0700 From: Yang Weijiang To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com, like.xu.linux@gmail.com, vkuznets@redhat.com, wei.w.wang@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yang Weijiang Subject: [PATCH v10 14/16] KVM: x86/vmx: Flip Arch LBREn bit on guest state change Date: Fri, 22 Apr 2022 03:55:07 -0400 Message-Id: <20220422075509.353942-15-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220422075509.353942-1-weijiang.yang@intel.com> References: <20220422075509.353942-1-weijiang.yang@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Per spec:"IA32_LBR_CTL.LBREn is saved and cleared on #SMI, and restored on RSM. On a warm reset, all LBR MSRs, including IA32_LBR_DEPTH, have their values preserved. However, IA32_LBR_CTL.LBREn is cleared to 0, disabling LBRs." So clear Arch LBREn bit on #SMI and restore it on RSM manully, also clear the bit when guest does warm reset. Signed-off-by: Yang Weijiang --- arch/x86/kvm/vmx/vmx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8c2a4c6923a2..d58d50730efa 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4588,6 +4588,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) if (!init_event) { if (static_cpu_has(X86_FEATURE_ARCH_LBR)) vmcs_write64(GUEST_IA32_LBR_CTL, 0); + } else { + flip_arch_lbr_ctl(vcpu, false); } } @@ -7699,6 +7701,7 @@ static int vmx_enter_smm(struct kvm_vcpu *vcpu, char *smstate) vmx->nested.smm.vmxon = vmx->nested.vmxon; vmx->nested.vmxon = false; vmx_clear_hlt(vcpu); + flip_arch_lbr_ctl(vcpu, false); return 0; } @@ -7720,6 +7723,7 @@ static int vmx_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) vmx->nested.nested_run_pending = 1; vmx->nested.smm.guest_mode = false; } + flip_arch_lbr_ctl(vcpu, true); return 0; }