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Thu, 28 Apr 2022 07:11:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT042.mail.protection.outlook.com (10.13.173.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Thu, 28 Apr 2022 07:11:15 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 28 Apr 2022 02:11:12 -0500 From: Manali Shukla To: , CC: Subject: [kvm-unit-tests PATCH v4 4/8] x86: Improve set_mmu_range() to implement npt Date: Thu, 28 Apr 2022 07:08:47 +0000 Message-ID: <20220428070851.21985-5-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220428070851.21985-1-manali.shukla@amd.com> References: <20220428070851.21985-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b53f636-bad8-4a49-248c-08da28e64923 X-MS-TrafficTypeDiagnostic: DM6PR12MB2873:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 07:11:15.9881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b53f636-bad8-4a49-248c-08da28e64923 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2873 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org If U/S bit is "0" for all page table entries, all these pages are considered as supervisor pages. By default, pte_opt_mask is set to "0" for all npt test cases, which sets U/S bit in all PTEs to "0". Any nested page table accesses performed by the MMU are treated as user acesses. So while implementing a nested page table dynamically, PT_USER_MASK needs to be enabled for all npt entries. set_mmu_range() function is improved based on above analysis. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- lib/x86/vm.c | 37 +++++++++++++++++++++++++++---------- lib/x86/vm.h | 3 +++ 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 25a4f5f..b555d5b 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -4,7 +4,7 @@ #include "alloc_page.h" #include "smp.h" -static pteval_t pte_opt_mask; +static pteval_t pte_opt_mask, prev_pte_opt_mask; pteval_t *install_pte(pgd_t *cr3, int pte_level, @@ -140,16 +140,33 @@ bool any_present_pages(pgd_t *cr3, void *virt, size_t len) return false; } -static void setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len) +void set_pte_opt_mask() +{ + prev_pte_opt_mask = pte_opt_mask; + pte_opt_mask = PT_USER_MASK; +} + +void reset_pte_opt_mask() +{ + pte_opt_mask = prev_pte_opt_mask; +} + +void setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len, bool nested_mmu) { u64 max = (u64)len + (u64)start; u64 phys = start; - while (phys + LARGE_PAGE_SIZE <= max) { - install_large_page(cr3, phys, (void *)(ulong)phys); - phys += LARGE_PAGE_SIZE; - } - install_pages(cr3, phys, max - phys, (void *)(ulong)phys); + if (nested_mmu == false) { + while (phys + LARGE_PAGE_SIZE <= max) { + install_large_page(cr3, phys, (void *)(ulong)phys); + phys += LARGE_PAGE_SIZE; + } + install_pages(cr3, phys, max - phys, (void *)(ulong)phys); + } else { + set_pte_opt_mask(); + install_pages(cr3, phys, len, (void *)(ulong)phys); + reset_pte_opt_mask(); + } } static void set_additional_vcpu_vmregs(struct vm_vcpu_info *info) @@ -176,10 +193,10 @@ void *setup_mmu(phys_addr_t end_of_memory, void *opt_mask) if (end_of_memory < (1ul << 32)) end_of_memory = (1ul << 32); /* map mmio 1:1 */ - setup_mmu_range(cr3, 0, end_of_memory); + setup_mmu_range(cr3, 0, end_of_memory, false); #else - setup_mmu_range(cr3, 0, (2ul << 30)); - setup_mmu_range(cr3, 3ul << 30, (1ul << 30)); + setup_mmu_range(cr3, 0, (2ul << 30), false); + setup_mmu_range(cr3, 3ul << 30, (1ul << 30), false); init_alloc_vpage((void*)(3ul << 30)); #endif diff --git a/lib/x86/vm.h b/lib/x86/vm.h index 4c6dff9..fbb657f 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -37,6 +37,9 @@ pteval_t *install_pte(pgd_t *cr3, pteval_t *install_large_page(pgd_t *cr3, phys_addr_t phys, void *virt); void install_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt); bool any_present_pages(pgd_t *cr3, void *virt, size_t len); +void set_pte_opt_mask(void); +void reset_pte_opt_mask(void); +void setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len, bool nested_mmu); static inline void *current_page_table(void) {