diff mbox series

[kvm-unit-tests,2/3] x86: Skip running test when pmu is disabled

Message ID 20220609083916.36658-3-weijiang.yang@intel.com (mailing list archive)
State New, archived
Headers show
Series Fix up test failures induced by !enable_pmu | expand

Commit Message

Yang, Weijiang June 9, 2022, 8:39 a.m. UTC 
Read MSR_IA32_PERF_CAPABILITIES triggers #GP when pmu is disabled
by enable_pmu=0 in KVM. Let's check whether pmu is available before
issue msr reading to avoid the #GP.

Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
 x86/pmu_lbr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Like Xu June 9, 2022, 11:57 p.m. UTC | #1 
On 9/6/2022 4:39 pm, Yang Weijiang wrote:
> +	perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);

Nit, check the PDCM bit before accessing this MSR.
Yang, Weijiang June 10, 2022, 1:40 a.m. UTC | #2 
On 6/10/2022 7:57 AM, Like Xu wrote:
> On 9/6/2022 4:39 pm, Yang Weijiang wrote:
>> +    perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);
>
> Nit, check the PDCM bit before accessing this MSR.
Thanks, I'll add the check.
diff mbox series

Patch

diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c
index 688634d..835a7bb 100644
--- a/x86/pmu_lbr.c
+++ b/x86/pmu_lbr.c
@@ -74,13 +74,15 @@  int main(int ac, char **av)
 		return 0;
 	}
 
-	perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);
 	eax.full = id.a;
 
 	if (!eax.split.version_id) {
 		printf("No pmu is detected!\n");
 		return report_summary();
 	}
+
+	perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);
+
 	if (!(perf_cap & PMU_CAP_LBR_FMT)) {
 		printf("No LBR is detected!\n");
 		return report_summary();