| Message ID | 20220615084641.6977-2-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix up failures induced by !enable_pmu | expand |
On Wed, Jun 15, 2022, Yang Weijiang wrote: > When pmu is disabled in KVM by enable_pmu=0, bit 7 of guest > MSR_IA32_MISC_ENABLE is cleared, but the default value of > the MSR assumes pmu is always available, this leads to test > failure. Change the logic to make it aligned with KVM config. > > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> Paolo's more generic approach is preferable, though even that can be more generic. https://lore.kernel.org/all/20220520183207.7952-1-pbonzini@redhat.com > --- > x86/msr.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/x86/msr.c b/x86/msr.c > index 44fbb3b..fc05d6c 100644 > --- a/x86/msr.c > +++ b/x86/msr.c > @@ -34,7 +34,7 @@ struct msr_info msr_info[] = > MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), > MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), > // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 > - MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), > + MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51809, false), > MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), > MSR_TEST(MSR_FS_BASE, addr_64, true), > MSR_TEST(MSR_GS_BASE, addr_64, true), > @@ -59,6 +59,8 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) > */ > if (msr->index == MSR_EFER) > val |= orig; > + if (msr->index == MSR_IA32_MISC_ENABLE) > + val |= MSR_IA32_MISC_ENABLE_EMON & orig; > wrmsr(msr->index, val); > r = rdmsr(msr->index); > wrmsr(msr->index, orig); > -- > 2.31.1 >
On 6/17/2022 2:30 AM, Sean Christopherson wrote: > On Wed, Jun 15, 2022, Yang Weijiang wrote: >> When pmu is disabled in KVM by enable_pmu=0, bit 7 of guest >> MSR_IA32_MISC_ENABLE is cleared, but the default value of >> the MSR assumes pmu is always available, this leads to test >> failure. Change the logic to make it aligned with KVM config. >> >> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > Paolo's more generic approach is preferable, though even that can be more generic. > > https://lore.kernel.org/all/20220520183207.7952-1-pbonzini@redhat.com Saw it , thanks! Maybe I just need to help Paolo resend the patch in my series. > >> --- >> x86/msr.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/x86/msr.c b/x86/msr.c >> index 44fbb3b..fc05d6c 100644 >> --- a/x86/msr.c >> +++ b/x86/msr.c >> @@ -34,7 +34,7 @@ struct msr_info msr_info[] = >> MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), >> MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), >> // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 >> - MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), >> + MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51809, false), >> MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), >> MSR_TEST(MSR_FS_BASE, addr_64, true), >> MSR_TEST(MSR_GS_BASE, addr_64, true), >> @@ -59,6 +59,8 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) >> */ >> if (msr->index == MSR_EFER) >> val |= orig; >> + if (msr->index == MSR_IA32_MISC_ENABLE) >> + val |= MSR_IA32_MISC_ENABLE_EMON & orig; >> wrmsr(msr->index, val); >> r = rdmsr(msr->index); >> wrmsr(msr->index, orig); >> -- >> 2.31.1 >>
diff --git a/x86/msr.c b/x86/msr.c index 44fbb3b..fc05d6c 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -34,7 +34,7 @@ struct msr_info msr_info[] = MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), + MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51809, false), MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), MSR_TEST(MSR_FS_BASE, addr_64, true), MSR_TEST(MSR_GS_BASE, addr_64, true), @@ -59,6 +59,8 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) */ if (msr->index == MSR_EFER) val |= orig; + if (msr->index == MSR_IA32_MISC_ENABLE) + val |= MSR_IA32_MISC_ENABLE_EMON & orig; wrmsr(msr->index, val); r = rdmsr(msr->index); wrmsr(msr->index, orig);
When pmu is disabled in KVM by enable_pmu=0, bit 7 of guest MSR_IA32_MISC_ENABLE is cleared, but the default value of the MSR assumes pmu is always available, this leads to test failure. Change the logic to make it aligned with KVM config. Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- x86/msr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)