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Tue, 28 Jun 2022 11:40:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT018.mail.protection.outlook.com (10.13.176.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5373.15 via Frontend Transport; Tue, 28 Jun 2022 11:40:46 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 28 Jun 2022 06:40:44 -0500 From: Manali Shukla To: , CC: Subject: [kvm-unit-tests PATCH v5 4/8] x86: Improve set_mmu_range() to implement npt Date: Tue, 28 Jun 2022 11:38:49 +0000 Message-ID: <20220628113853.392569-5-manali.shukla@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220628113853.392569-1-manali.shukla@amd.com> References: <20220628113853.392569-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b402b92-bbfc-4b25-0fc0-08da58fb0ac2 X-MS-TrafficTypeDiagnostic: BN8PR12MB3299:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 11:40:46.6247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b402b92-bbfc-4b25-0fc0-08da58fb0ac2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3299 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Modify setup_mmu_range() to implement nested page table dynamically by setting PT_USER_MASK bit for all NPT pages because any nested page table accesses performed by the MMU are treated as user accesses. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- lib/x86/vm.c | 25 +++++++++++++++++++++---- lib/x86/vm.h | 8 ++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/lib/x86/vm.c b/lib/x86/vm.c index 25a4f5f..46c36e5 100644 --- a/lib/x86/vm.c +++ b/lib/x86/vm.c @@ -140,16 +140,33 @@ bool any_present_pages(pgd_t *cr3, void *virt, size_t len) return false; } -static void setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len) +void __setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len, + unsigned long long mmu_flags) { + u64 orig_opt_mask = pte_opt_mask; u64 max = (u64)len + (u64)start; u64 phys = start; - while (phys + LARGE_PAGE_SIZE <= max) { - install_large_page(cr3, phys, (void *)(ulong)phys); - phys += LARGE_PAGE_SIZE; + /* + * Allocate 4k pages only for nested page table, PT_USER_MASK needs to + * be enabled only for nested pages. + */ + if (mmu_flags & IS_NESTED_MMU) + pte_opt_mask |= PT_USER_MASK; + + if (mmu_flags & USE_HUGEPAGES) { + while (phys + LARGE_PAGE_SIZE <= max) { + install_large_page(cr3, phys, (void *)(ulong)phys); + phys += LARGE_PAGE_SIZE; + } } install_pages(cr3, phys, max - phys, (void *)(ulong)phys); + + pte_opt_mask = orig_opt_mask; +} + +static inline void setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len) { + __setup_mmu_range(cr3, start, len, USE_HUGEPAGES); } static void set_additional_vcpu_vmregs(struct vm_vcpu_info *info) diff --git a/lib/x86/vm.h b/lib/x86/vm.h index 4c6dff9..2df19e3 100644 --- a/lib/x86/vm.h +++ b/lib/x86/vm.h @@ -4,6 +4,10 @@ #include "processor.h" #include "asm/page.h" #include "asm/io.h" +#include "asm/bitops.h" + +#define IS_NESTED_MMU BIT(0) +#define USE_HUGEPAGES BIT(1) void setup_5level_page_table(void); @@ -37,6 +41,10 @@ pteval_t *install_pte(pgd_t *cr3, pteval_t *install_large_page(pgd_t *cr3, phys_addr_t phys, void *virt); void install_pages(pgd_t *cr3, phys_addr_t phys, size_t len, void *virt); bool any_present_pages(pgd_t *cr3, void *virt, size_t len); +void set_pte_opt_mask(void); +void reset_pte_opt_mask(void); +void __setup_mmu_range(pgd_t *cr3, phys_addr_t start, size_t len, + unsigned long long mmu_flags); static inline void *current_page_table(void) {