From patchwork Tue Aug 2 07:47:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 12934310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E900CC00140 for ; Tue, 2 Aug 2022 07:49:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236190AbiHBHtU (ORCPT ); Tue, 2 Aug 2022 03:49:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236161AbiHBHtB (ORCPT ); Tue, 2 Aug 2022 03:49:01 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51004BD36 for ; Tue, 2 Aug 2022 00:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659426539; x=1690962539; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=llgtqfRW17L8raNa4ie9Vz+9QCbmcsWc5ycFx5pSCnM=; b=e/PqihLmXENYob+xUf+t+Xow0q5GdR9FusojiYhWeDBsGqltS6CMzQXc 5gQX5lQpt+k4v/DI6CjQvMB2TDk76WFSAbeiwgWXb+W85HmYxBDSludKI DVeCd+s/32daD23gPUNXuAL36munQx1SIdXpPFojHsJ/4AIJClOnXPzbE +1fPSVHEmqR+0XqQE5qZytI74RBF3KAKxRBBYvtvW5kMjEYkEmBYptllY txeNaMRdnY5s7dy/VU4f2+fqjNBwQZcDEvot2bEXSYwblXeE1i1TGZl9y YorKJ//IAiOxHb8vLGxJBAZAu4i+77eduQQb4vNma2j0XXaX8QPLezQFL g==; X-IronPort-AV: E=McAfee;i="6400,9594,10426"; a="286908604" X-IronPort-AV: E=Sophos;i="5.93,210,1654585200"; d="scan'208";a="286908604" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2022 00:48:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,210,1654585200"; d="scan'208";a="630604023" Received: from lxy-dell.sh.intel.com ([10.239.48.38]) by orsmga008.jf.intel.com with ESMTP; 02 Aug 2022 00:48:55 -0700 From: Xiaoyao Li To: Paolo Bonzini , Isaku Yamahata , Gerd Hoffmann , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= , Richard Henderson , "Michael S . Tsirkin" , Marcel Apfelbaum , Cornelia Huck , Marcelo Tosatti , Laszlo Ersek , Eric Blake Cc: Connor Kuehl , erdemaktas@google.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, seanjc@google.com, xiaoyao.li@intel.com Subject: [PATCH v1 15/40] i386/tdx: Add property sept-ve-disable for tdx-guest object Date: Tue, 2 Aug 2022 15:47:25 +0800 Message-Id: <20220802074750.2581308-16-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220802074750.2581308-1-xiaoyao.li@intel.com> References: <20220802074750.2581308-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Bit 28, named SEPT_VE_DISABLE, disables EPT violation conversion to #VE on guest TD access of PENDING pages when set to 1. Some guest OS (e.g., Linux TD guest) may require this bit set as 1. Otherwise refuse to boot. Add sept-ve-disable property for tdx-guest object, for user to configure this bit. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- qapi/qom.json | 4 +++- target/i386/kvm/tdx.c | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/qapi/qom.json b/qapi/qom.json index 38177848abc1..2a5486bfed3e 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -835,10 +835,12 @@ # # Properties for tdx-guest objects. # +# @sept-ve-disable: bit 28 of TD attributes (default: 0) +# # Since: 7.2 ## { 'struct': 'TdxGuestProperties', - 'data': { }} + 'data': { '*sept-ve-disable': 'bool' } } ## # @ObjectType: diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index ecb0205651bd..bf57f270ac9d 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -30,6 +30,8 @@ (1U << KVM_FEATURE_PV_SCHED_YIELD) | \ (1U << KVM_FEATURE_MSI_EXT_DEST_ID)) +#define TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE BIT_ULL(28) + #define TDX_ATTRIBUTES_MAX_BITS 64 static FeatureMask tdx_attrs_ctrl_fields[TDX_ATTRIBUTES_MAX_BITS] = { @@ -490,6 +492,24 @@ out: return r; } +static bool tdx_guest_get_sept_ve_disable(Object *obj, Error **errp) +{ + TdxGuest *tdx = TDX_GUEST(obj); + + return !!(tdx->attributes & TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE); +} + +static void tdx_guest_set_sept_ve_disable(Object *obj, bool value, Error **errp) +{ + TdxGuest *tdx = TDX_GUEST(obj); + + if (value) { + tdx->attributes |= TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE; + } else { + tdx->attributes &= ~TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE; + } +} + /* tdx guest */ OBJECT_DEFINE_TYPE_WITH_INTERFACES(TdxGuest, tdx_guest, @@ -505,6 +525,10 @@ static void tdx_guest_init(Object *obj) qemu_mutex_init(&tdx->lock); tdx->attributes = 0; + + object_property_add_bool(obj, "sept-ve-disable", + tdx_guest_get_sept_ve_disable, + tdx_guest_set_sept_ve_disable); } static void tdx_guest_finalize(Object *obj)