From patchwork Fri Aug 5 00:41:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Koller X-Patchwork-Id: 12936816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FE25C25B0C for ; Fri, 5 Aug 2022 00:41:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234270AbiHEAls (ORCPT ); Thu, 4 Aug 2022 20:41:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233821AbiHEAlq (ORCPT ); Thu, 4 Aug 2022 20:41:46 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E86A36FA03 for ; Thu, 4 Aug 2022 17:41:45 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id e15-20020a17090301cf00b0016dc94ddcc5so709585plh.3 for ; Thu, 04 Aug 2022 17:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc; bh=IkUE99B0TchNS4vqhItmmclxhXXwJ9wxAc8kOQ5+evM=; b=iVfcJW8RlHTsp+7/8Ai9Ar6TcPX/EvMkfx9Ea9osF8B/WeFcKJTGR5MvNNv1C9aR3D dPpsi/u/rJgjH15v3faO9zC5EdKesI2rs6biTyr0ayp3x4Opjln4sViOrhtDPkYsZN7/ zHVUvjuftQKLseSsX4XYZlVEgF6fOEz2Xj8E/EaEbrafUJIVz6AUoLSnACjkTHbWvkHQ f5aJ8ht6Mq6aHZvmE4wyLtd09SO09NWmoNiCvYnmZXQotuzZoZUKbZu3Hn0r4aDZvoYI UXPhVBkqEinpEnZKG2rptUcvNeJS4pVhflPwPB9WGEvk98udF50S2IvLo9GRJhqGi9GH BhQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc; bh=IkUE99B0TchNS4vqhItmmclxhXXwJ9wxAc8kOQ5+evM=; b=Z+7i+mBtDSNsxZBcyff+3xi1eFe0Q2njgy6x2U8VC5Niw5+q86IdZSmkufw+sf0WZA sYIqeQ9If9U62eQo6eTWqu3nEgfiiKWx6tivebr0/vkmUDaWncU1Cqc6fJi65J2AHTlS peCc+czppBHpeG79DryVsAxlyoU2KlDWdJOifrAGGGpsFfzh6SywljWG6euAJrGEU351 9whUi2pURA9/GQ8TkXapDHvmSS9bP2kFCLtx2QD9BarKADaiBXUMEC8+NkKmJU01vy89 JLDk95rAGUvmNBMfYQSItT4s0fqGvxfFZ7V/JmP0WTyAHNCXlfV15jjiDB+Fq3kN1huj Ws6Q== X-Gm-Message-State: ACgBeo1Cntd2zWEz5JIXfcYlKPFitrzIW3FWKsRgvvnppkAaqBcMydCF 97ExFChOmtaZ5cVi1vSoIsL5SDD06b+rWfxTjaJXzQiOVjPooP86/CLelGNnKAKdSc2PYMhqpux +oQB9SLSo/6soNuQL6j5NtdUH5vkVkKiDDL49Lls5nktE81gHbfqmw8s4xxZJi+k= X-Google-Smtp-Source: AA6agR4TcLN6Lga7RRZ0+dyIKf0ldH3fBJqtB88WLNxRgIPNyZKd3Bc+sF7uqhYAz2fvChCj+ulwcPDPdw6XaQ== X-Received: from ricarkol2.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:62fe]) (user=ricarkol job=sendgmr) by 2002:a17:902:a616:b0:16d:b3cf:9fe3 with SMTP id u22-20020a170902a61600b0016db3cf9fe3mr4127366plq.99.1659660105374; Thu, 04 Aug 2022 17:41:45 -0700 (PDT) Date: Thu, 4 Aug 2022 17:41:38 -0700 In-Reply-To: <20220805004139.990531-1-ricarkol@google.com> Message-Id: <20220805004139.990531-3-ricarkol@google.com> Mime-Version: 1.0 References: <20220805004139.990531-1-ricarkol@google.com> X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [kvm-unit-tests PATCH v3 2/3] arm: pmu: Reset the pmu registers before starting some tests From: Ricardo Koller To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, andrew.jones@linux.dev Cc: maz@kernel.org, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com, Ricardo Koller Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some registers like the PMOVS reset to an architecturally UNKNOWN value. Most tests expect them to be reset (mostly zeroed) using pmu_reset(). Add a pmu_reset() on all the tests that need one. As a bonus, fix a couple of comments related to the register state before a sub-test. Reviewed-by: Eric Auger Signed-off-by: Ricardo Koller --- arm/pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arm/pmu.c b/arm/pmu.c index 4c601b05..12e7d84e 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -826,7 +826,7 @@ static void test_overflow_interrupt(void) write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); isb(); - /* interrupts are disabled */ + /* interrupts are disabled (PMINTENSET_EL1 == 0) */ mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); report(expect_interrupts(0), "no overflow interrupt after preset"); @@ -842,7 +842,7 @@ static void test_overflow_interrupt(void) isb(); report(expect_interrupts(0), "no overflow interrupt after counting"); - /* enable interrupts */ + /* enable interrupts (PMINTENSET_EL1 <= ALL_SET) */ pmu_reset_stats(); @@ -890,6 +890,7 @@ static bool check_cycles_increase(void) bool success = true; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ @@ -944,6 +945,7 @@ static bool check_cpi(int cpi) uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */