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Wed, 10 Aug 2022 05:21:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT006.mail.protection.outlook.com (10.13.174.246) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5525.11 via Frontend Transport; Wed, 10 Aug 2022 05:21:03 +0000 Received: from bhadra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 10 Aug 2022 00:20:41 -0500 From: Manali Shukla To: , CC: , Subject: [kvm-unit-tests PATCH v2 1/4] x86: nSVM: Add an exception test framework and tests Date: Wed, 10 Aug 2022 05:20:27 +0000 Message-ID: <20220810052027.7575-1-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220810050738.7442-1-manali.shukla@amd.com> References: <20220810050738.7442-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a73fcf63-8eeb-416c-0d9b-08da7a901f13 X-MS-TrafficTypeDiagnostic: SJ0PR12MB7082:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2022 05:21:03.9380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a73fcf63-8eeb-416c-0d9b-08da7a901f13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7082 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Set up a test framework that verifies an exception occurring in L2 is forwarded to the right place (L1 or L2). It adds an exception test array and exception callbacks to that array. Tests two conditions for each exception. 1) Exception generated in L2, is handled by L2 when L2 exception handler is registered. 2) Exception generated in L2, is handled by L1 when intercept exception bit map is set in L1. Add testing for below exceptions: (#GP, #UD, #DE, #DB, #AC) 1. #GP is generated in c by non-canonical access in L2. 2. #UD is generated by calling "ud2" instruction in L2. 3. #DE is generated using instrumented code which generates divide by zero condition. 4. #DB is generated by setting TF bit before entering to L2. 5. #AC is genrated by writing 8 bytes to 4 byte aligned address in L2 user mode when AM bit is set in CR0 register and AC bit is set in RFLAGS. Signed-off-by: Manali Shukla --- x86/svm_tests.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/x86/svm_tests.c b/x86/svm_tests.c index e2ec954..7544034 100644 --- a/x86/svm_tests.c +++ b/x86/svm_tests.c @@ -10,6 +10,7 @@ #include "isr.h" #include "apic.h" #include "delay.h" +#include "x86/usermode.h" #define SVM_EXIT_MAX_DR_INTERCEPT 0x3f @@ -3289,6 +3290,118 @@ static void svm_intr_intercept_mix_smi(void) svm_intr_intercept_mix_run_guest(NULL, SVM_EXIT_SMI); } +static void svm_l2_gp_test(struct svm_test *test) +{ + *(volatile u64 *)NONCANONICAL = 0; +} + +static void svm_l2_ud_test(struct svm_test *test) +{ + asm volatile ("ud2"); +} + +static void svm_l2_de_test(struct svm_test *test) +{ + asm volatile ( + "xor %%eax, %%eax\n\t" + "xor %%ebx, %%ebx\n\t" + "xor %%edx, %%edx\n\t" + "idiv %%ebx\n\t" + ::: "eax", "ebx", "edx"); +} + +static void svm_l2_db_test(struct svm_test *test) +{ + write_rflags(read_rflags() | X86_EFLAGS_TF); +} + +static uint64_t usermode_callback(void) +{ + /* + * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. + * Disclaimer: It is assumed that the stack pointer is aligned + * on a 16-byte boundary as x86_64 stacks should be. + */ + asm volatile("movq $0, -0x4(%rsp)"); + + return 0; +} + +static void svm_l2_ac_test(struct svm_test *test) +{ + bool hit_ac = false; + + write_cr0(read_cr0() | X86_CR0_AM); + write_rflags(read_rflags() | X86_EFLAGS_AC); + + run_in_user(usermode_callback, AC_VECTOR, 0, 0, 0, 0, &hit_ac); + report(hit_ac, "Usermode #AC handled in L2"); + vmmcall(); +} + +struct svm_exception_test { + u8 vector; + void (*guest_code)(struct svm_test*); +}; + +struct svm_exception_test svm_exception_tests[] = { + { GP_VECTOR, svm_l2_gp_test }, + { UD_VECTOR, svm_l2_ud_test }, + { DE_VECTOR, svm_l2_de_test }, + { DB_VECTOR, svm_l2_db_test }, + { AC_VECTOR, svm_l2_ac_test }, +}; + +static u8 svm_exception_test_vector; + +static void svm_exception_handler(struct ex_regs *regs) +{ + report(regs->vector == svm_exception_test_vector, + "Handling %s in L2's exception handler", + exception_mnemonic(svm_exception_test_vector)); + vmmcall(); +} + +static void handle_exception_in_l2(u8 vector) +{ + handler old_handler = handle_exception(vector, svm_exception_handler); + svm_exception_test_vector = vector; + + report(svm_vmrun() == SVM_EXIT_VMMCALL, + "%s handled by L2", exception_mnemonic(vector)); + + handle_exception(vector, old_handler); +} + +static void handle_exception_in_l1(u32 vector) +{ + u32 old_ie = vmcb->control.intercept_exceptions; + + vmcb->control.intercept_exceptions |= (1ULL << vector); + + report(svm_vmrun() == (SVM_EXIT_EXCP_BASE + vector), + "%s handled by L1", exception_mnemonic(vector)); + + vmcb->control.intercept_exceptions = old_ie; +} + +static void svm_exception_test(void) +{ + struct svm_exception_test *t; + int i; + + for (i = 0; i < ARRAY_SIZE(svm_exception_tests); i++) { + t = &svm_exception_tests[i]; + test_set_guest(t->guest_code); + + handle_exception_in_l2(t->vector); + vmcb_ident(vmcb); + + handle_exception_in_l1(t->vector); + vmcb_ident(vmcb); + } +} + struct svm_test svm_tests[] = { { "null", default_supported, default_prepare, default_prepare_gif_clear, null_test, @@ -3389,6 +3502,7 @@ struct svm_test svm_tests[] = { TEST(svm_nm_test), TEST(svm_int3_test), TEST(svm_into_test), + TEST(svm_exception_test), TEST(svm_lbrv_test0), TEST(svm_lbrv_test1), TEST(svm_lbrv_test2),