diff mbox series

[kvm-unit-tests,v4,2/4] arm: pmu: Add reset_pmu() for 32-bit arm

Message ID 20220811185210.234711-3-ricarkol@google.com (mailing list archive)
State New, archived
Headers show
Series arm: pmu: Fixes for bare metal | expand

Commit Message

Ricardo Koller Aug. 11, 2022, 6:52 p.m. UTC 
Add a 32-bit arm version of reset_pmu(). Add all the necessary register
definitions as well.

Signed-off-by: Ricardo Koller <ricarkol@google.com>
---
 arm/pmu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
diff mbox series

Patch

diff --git a/arm/pmu.c b/arm/pmu.c
index 4c601b05..a5260178 100644
--- a/arm/pmu.c
+++ b/arm/pmu.c
@@ -93,7 +93,10 @@  static struct pmu pmu;
 #define PMSELR       __ACCESS_CP15(c9, 0, c12, 5)
 #define PMXEVTYPER   __ACCESS_CP15(c9, 0, c13, 1)
 #define PMCNTENSET   __ACCESS_CP15(c9, 0, c12, 1)
+#define PMCNTENCLR   __ACCESS_CP15(c9, 0, c12, 2)
+#define PMOVSR       __ACCESS_CP15(c9, 0, c12, 3)
 #define PMCCNTR32    __ACCESS_CP15(c9, 0, c13, 0)
+#define PMINTENCLR   __ACCESS_CP15(c9, 0, c14, 2)
 #define PMCCNTR64    __ACCESS_CP15_64(0, c9)
 
 static inline uint32_t get_id_dfr0(void) { return read_sysreg(ID_DFR0); }
@@ -145,6 +148,19 @@  static inline void precise_instrs_loop(int loop, uint32_t pmcr)
 	: "cc");
 }
 
+static void pmu_reset(void)
+{
+	/* reset all counters, counting disabled at PMCR level*/
+	set_pmcr(pmu.pmcr_ro | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_P);
+	/* Disable all counters */
+	write_sysreg(ALL_SET, PMCNTENCLR);
+	/* clear overflow reg */
+	write_sysreg(ALL_SET, PMOVSR);
+	/* disable overflow interrupts on all counters */
+	write_sysreg(ALL_SET, PMINTENCLR);
+	isb();
+}
+
 /* event counter tests only implemented for aarch64 */
 static void test_event_introspection(void) {}
 static void test_event_counter_config(void) {}