Message ID | 20220921214439.1491510-15-stillson@rivosinc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Wed, 21 Sep 2022 14:54:55 -0700 (PDT) Received: from stillson.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k7-20020aa79727000000b005484d133127sm2634536pfg.129.2022.09.21.14.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Sep 2022 14:54:55 -0700 (PDT) From: Chris Stillson <stillson@rivosinc.com> Cc: Vincent Chen <vincent.chen@sifive.com>, Greentime Hu <greentime.hu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Eric Biederman <ebiederm@xmission.com>, Kees Cook <keescook@chromium.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Oleg Nesterov <oleg@redhat.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, Guo Ren <guoren@kernel.org>, Conor Dooley <conor.dooley@microchip.com>, Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>, Chris Stillson <stillson@rivosinc.com>, Paolo Bonzini <pbonzini@redhat.com>, Qinglin Pan <panqinglin2020@iscas.ac.cn>, Alexandre Ghiti <alexandre.ghiti@canonical.com>, Arnd Bergmann <arnd@arndb.de>, Heiko Stuebner <heiko@sntech.de>, Jisheng Zhang <jszhang@kernel.org>, Dao Lu <daolu@rivosinc.com>, Sunil V L <sunilvl@ventanamicro.com>, Nick Knight <nick.knight@sifive.com>, Han-Kuan Chen <hankuan.chen@sifive.com>, Changbin Du <changbin.du@intel.com>, Li Zhengyu <lizhengyu3@huawei.com>, Ard Biesheuvel <ardb@kernel.org>, Tsukasa OI <research_trasio@irq.a4lg.com>, Yury Norov <yury.norov@gmail.com>, Frederic Weisbecker <frederic@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Vitaly Wool <vitaly.wool@konsulko.com>, Myrtle Shah <gatecat@ds0.me>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>, Janosch Frank <frankja@linux.ibm.com>, Huacai Chen <chenhuacai@kernel.org>, Alexey Dobriyan <adobriyan@gmail.com>, Christian Brauner <brauner@kernel.org>, Vincenzo Frascino <Vincenzo.Frascino@arm.com>, Eugene Syromiatnikov <esyr@redhat.com>, Colin Cross <ccross@google.com>, Peter Collingbourne <pcc@google.com>, Andrew Morton <akpm@linux-foundation.org>, Barret Rhoden <brho@google.com>, Suren Baghdasaryan <surenb@google.com>, Davidlohr Bueso <dave@stgolabs.net>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Date: Wed, 21 Sep 2022 14:43:57 -0700 Message-Id: <20220921214439.1491510-15-stillson@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com> References: <20220921214439.1491510-1-stillson@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; 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[v12,01/17] riscv: Rename __switch_to_aux -> fpu
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diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6f59ec64175e..b242ed155262 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -35,6 +35,7 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * Increse this to higher value as kernel support more ISA extensions.