From patchwork Wed Sep 21 21:43:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Stillson X-Patchwork-Id: 12984203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8A30C32771 for ; Wed, 21 Sep 2022 21:48:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229942AbiIUVsE (ORCPT ); Wed, 21 Sep 2022 17:48:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230329AbiIUVsC (ORCPT ); Wed, 21 Sep 2022 17:48:02 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6991A6C45 for ; Wed, 21 Sep 2022 14:47:57 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id rt12so5380056pjb.1 for ; Wed, 21 Sep 2022 14:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=olGNKHmEJH+71TMcZkD0ZGQWhJ2EEH99STiEKZ89va4=; b=aVq4hID8qEEukk8LuM4VePyf26vjYh9KZTX7mzS9qcDL8PHSNrRR7ZwkZ/XF/AQsV2 jccmz8kP+YoGi8mSPUG8K/V4PadVsR+EPGhUyQekfq5Q12WZzSzaeWU3gkr7+8R/YUxk xBCiLx5/1SCyaiz+I8nY2qGQNTQMe5/4+6quaBcXGgG+3ke/Ia2EYnPnT/lOlwfLWmfW YHQccNWKNGyXSk8f8MGgoYC14/ojtaJ/aM1MN7AiO45O/1mIsDDqX+OUeNr2/a9V7hrq CxR6BGDofbeTUmFDzfhJBLov7b+fv78xG2X/fBnvVWkGPTeyGCf2gbE+WzAsABcdJTYD QxYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=olGNKHmEJH+71TMcZkD0ZGQWhJ2EEH99STiEKZ89va4=; b=cz2c3k4tzT8T6ew3CzH42ui8SLR8Kj5x4dKqyWUbQ4QtMsHSYokLqISM0VrtLFNfCm dQJ5q+aBl4oHnpk4sI+VDlcoY219E8jd4VKVVlZbNxMbWkLLL1A9LNDAp0Wj1w6kBP7E mqYAcMXefkAvqS3y5E//BidwA+bgIIdRYLWTWQ/VQIWMpQyCDgeGG6sq8vku095TnJ7W UjNIP8r9k0+S/BtIbBEX5joldR8CXInh4W1zm7rivf6EV1Hq+08eATV1/aGrvUfhLWJL z8TmTfL4h8anONdeG6GFRbimJ9Wok4uHQCbuCm0vockcEVqyTRh6WaIo5snmUDwAPQNF eryg== X-Gm-Message-State: ACrzQf3f9o2hc7TbF5bXsXx9D6LlLmSSxtAi4ZobjK97n3O72bYfZoM4 cyBLihw3RFVhDRptVvjVfS/CNg== X-Google-Smtp-Source: AMsMyM7gHe/KjK5UY39UWIx1gHdtzlkS/LQsxKDnen4yyLCy3GcJ1fJbnq0JpL5vfJJnS/DB+6/vEQ== X-Received: by 2002:a17:903:244b:b0:178:1c88:4a4c with SMTP id l11-20020a170903244b00b001781c884a4cmr76075pls.95.1663796876749; Wed, 21 Sep 2022 14:47:56 -0700 (PDT) Received: from stillson.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k7-20020aa79727000000b005484d133127sm2634536pfg.129.2022.09.21.14.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Sep 2022 14:47:56 -0700 (PDT) From: Chris Stillson Cc: Greentime Hu , Guo Ren , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Anup Patel , Atish Patra , Oleg Nesterov , Guo Ren , Heinrich Schuchardt , Chris Stillson , Arnaud Pouliquen , Paolo Bonzini , Alexandre Ghiti , Arnd Bergmann , Heiko Stuebner , Jisheng Zhang , Dao Lu , Sunil V L , Ruinland Tsai , Han-Kuan Chen , Changbin Du , Li Zhengyu , Alexander Graf , Ard Biesheuvel , Tsukasa OI , Yury Norov , Nicolas Saenz Julienne , "Paul E. McKenney" , Frederic Weisbecker , Mark Rutland , Vitaly Wool , Myrtle Shah , Catalin Marinas , Will Deacon , Mark Brown , WANG Xuerui , Huacai Chen , Alexey Dobriyan , Christian Brauner , Suren Baghdasaryan , Peter Collingbourne , Colin Cross , Eugene Syromiatnikov , Andrew Morton , Barret Rhoden , Davidlohr Bueso , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features. Date: Wed, 21 Sep 2022 14:43:47 -0700 Message-Id: <20220921214439.1491510-5-stillson@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220921214439.1491510-1-stillson@rivosinc.com> References: <20220921214439.1491510-1-stillson@rivosinc.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h | 14 +++++ arch/riscv/kernel/cpufeature.c | 19 +++++++ arch/riscv/kernel/riscv_ksyms.c | 6 +++ arch/riscv/kernel/vector.S | 93 +++++++++++++++++++++++++++++++++ 4 files changed, 132 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/kernel/vector.S diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h new file mode 100644 index 000000000000..16304b0c6a6f --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include + +void rvv_enable(void); +void rvv_disable(void); + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8d4448c2d4f4..0487ab19b234 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,14 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); +#ifdef CONFIG_FPU +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); +#endif +#ifdef CONFIG_VECTOR +#include +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector); +unsigned long riscv_vsize __read_mostly; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -249,6 +257,16 @@ void __init riscv_fill_hwcap(void) if (j >= 0) static_branch_enable(&riscv_isa_ext_keys[j]); } + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + static_branch_enable(&cpu_hwcap_vector); + /* There are 32 vector registers with vlenb length. */ + rvv_enable(); + riscv_vsize = csr_read(CSR_VLENB) * 32; + rvv_disable(); + } +#endif } #ifdef CONFIG_RISCV_ALTERNATIVE @@ -328,3 +346,4 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, } } #endif +} diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksyms.c index 5ab1c7e1a6ed..3489d2a20ca3 100644 --- a/arch/riscv/kernel/riscv_ksyms.c +++ b/arch/riscv/kernel/riscv_ksyms.c @@ -15,3 +15,9 @@ EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(__memset); EXPORT_SYMBOL(__memcpy); EXPORT_SYMBOL(__memmove); + +#ifdef CONFIG_VECTOR +#include +EXPORT_SYMBOL(rvv_enable); +EXPORT_SYMBOL(rvv_disable); +#endif diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S new file mode 100644 index 000000000000..9f7dc70c4443 --- /dev/null +++ b/arch/riscv/kernel/vector.S @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2019 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include + +#define vstatep a0 +#define datap a1 +#define x_vstart t0 +#define x_vtype t1 +#define x_vl t2 +#define x_vcsr t3 +#define incr t4 +#define status t5 + +ENTRY(__vstate_save) + li status, SR_VS + csrs CSR_STATUS, status + + csrr x_vstart, CSR_VSTART + csrr x_vtype, CSR_VTYPE + csrr x_vl, CSR_VL + csrr x_vcsr, CSR_VCSR + vsetvli incr, x0, e8, m8, ta, ma + vse8.v v0, (datap) + add datap, datap, incr + vse8.v v8, (datap) + add datap, datap, incr + vse8.v v16, (datap) + add datap, datap, incr + vse8.v v24, (datap) + + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_S x_vl, RISCV_V_STATE_VL(vstatep) + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep) + + csrc CSR_STATUS, status + ret +ENDPROC(__vstate_save) + +ENTRY(__vstate_restore) + li status, SR_VS + csrs CSR_STATUS, status + + vsetvli incr, x0, e8, m8, ta, ma + vle8.v v0, (datap) + add datap, datap, incr + vle8.v v8, (datap) + add datap, datap, incr + vle8.v v16, (datap) + add datap, datap, incr + vle8.v v24, (datap) + + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_L x_vl, RISCV_V_STATE_VL(vstatep) + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep) + vsetvl x0, x_vl, x_vtype + csrw CSR_VSTART, x_vstart + csrw CSR_VCSR, x_vcsr + + csrc CSR_STATUS, status + ret +ENDPROC(__vstate_restore) + +ENTRY(rvv_enable) + li status, SR_VS + csrs CSR_STATUS, status + ret +ENDPROC(rvv_enable) + +ENTRY(rvv_disable) + li status, SR_VS + csrc CSR_STATUS, status + ret +ENDPROC(rvv_disable)