From patchwork Wed Oct 19 08:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxi Chen X-Patchwork-Id: 13011489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D260C433FE for ; Wed, 19 Oct 2022 08:57:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbiJSI5D (ORCPT ); Wed, 19 Oct 2022 04:57:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbiJSI40 (ORCPT ); Wed, 19 Oct 2022 04:56:26 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DEF652479; Wed, 19 Oct 2022 01:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666169565; x=1697705565; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aN1z8mG+6FtVyNG8T1B6yk4JgG7etoGpqzlwCguutHU=; b=RjHTlC5clSe6EgBqvr3QFVOpn22g9Q3pVRE4XFeBMMPBSJ41cUqWkASw /VzXldnn0tipfKpgqNHMTZHfkYNxgsAWUOw1YB49ks+mfR86r+PuH83pc u5VD9QrUZkuWjJwfTADviemQIdlN2/jLUFUhsQ0qWT/pCmfjoOwvgzwcw dezP8knaaeciF1iGq4dFwCBDybLs9k7rDuoxwE0c2vcjiqMKJNB7f5fSj PrCVvaNlB3F5xLmwJY98E5NXPG36y2N4UNOYrujE0s4xanujQwkSQL6zu ESZpHYiLZNTxBw3lc2EtT27HRcYDTqRpdMM5Bmpa53MmwPKkODHj/MSiS g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="286065913" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="286065913" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 01:47:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="804195844" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="804195844" Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 01:47:39 -0700 From: Jiaxi Chen To: kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, ndesaulniers@google.com, alexandre.belloni@bootlin.com, peterz@infradead.org, jiaxi.chen@linux.intel.com, jpoimboe@kernel.org, chang.seok.bae@intel.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, jmattson@google.com, sandipan.das@amd.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, fenghua.yu@intel.com, keescook@chromium.org, jane.malalane@citrix.com, nathan@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] x86: KVM: Enable CMPccXADD CPUID and expose it to guest Date: Wed, 19 Oct 2022 16:47:29 +0800 Message-Id: <20221019084734.3590760-2-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019084734.3590760-1-jiaxi.chen@linux.intel.com> References: <20221019084734.3590760-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org CMPccXADD is a new set of instructions in the latest Intel platform Sierra Forest. It includes a semaphore operation that can compare and add the operands if condition is met, which can improve database performance. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 7] This patch enables this CPUID in the kernel feature bits and expose it to guest OS. Signed-off-by: Jiaxi Chen --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ef4775c6db01..445626cb5779 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7065462378e2..3f745f6fdc43 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -657,7 +657,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); kvm_cpu_cap_mask(CPUID_7_1_EAX, - F(AVX_VNNI) | F(AVX512_BF16) + F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) ); kvm_cpu_cap_mask(CPUID_D_1_EAX,