Message ID | 20221024091223.42631-18-likexu@tencent.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | x86/pmu: Test case optimization, fixes and additions | expand |
On Mon, Oct 24, 2022, Like Xu wrote: > +static inline u32 fixed_counter_msr(unsigned int i) > +{ > + return MSR_CORE_PERF_FIXED_CTR0 + i; This should be added in a separate patch. > +} > + > +static inline void write_fixed_counter_value(unsigned int i, u64 value) > +{ > + wrmsr(fixed_counter_msr(i), value); > +} > + > +static inline void reset_all_gp_counters(void) > +{ > + unsigned int idx; > + > + for (idx = 0; idx < pmu_nr_gp_counters(); idx++) { > + write_gp_event_select(idx, 0); > + write_gp_counter_value(idx, 0); > + } > +} > + > +static inline void reset_all_fixed_counters(void) > +{ > + unsigned int idx; > + > + if (!pmu_nr_fixed_counters()) > + return; > + > + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); > + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) > + write_fixed_counter_value(idx, 0); > +} > + > +static inline void reset_all_counters(void) Prefix these with "pmu_" so that it's obvious what counters are being rese. > +{ > + reset_all_gp_counters(); > + reset_all_fixed_counters(); > +}
diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c index c0d100d..0ce1691 100644 --- a/lib/x86/pmu.c +++ b/lib/x86/pmu.c @@ -10,4 +10,5 @@ void pmu_init(void) pmu.perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES); pmu.msr_gp_counter_base = MSR_IA32_PERFCTR0; pmu.msr_gp_event_select_base = MSR_P6_EVNTSEL0; + reset_all_counters(); } \ No newline at end of file diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h index 7487a30..564b672 100644 --- a/lib/x86/pmu.h +++ b/lib/x86/pmu.h @@ -156,4 +156,42 @@ static inline bool pmu_use_full_writes(void) return gp_counter_base() == MSR_IA32_PMC0; } +static inline u32 fixed_counter_msr(unsigned int i) +{ + return MSR_CORE_PERF_FIXED_CTR0 + i; +} + +static inline void write_fixed_counter_value(unsigned int i, u64 value) +{ + wrmsr(fixed_counter_msr(i), value); +} + +static inline void reset_all_gp_counters(void) +{ + unsigned int idx; + + for (idx = 0; idx < pmu_nr_gp_counters(); idx++) { + write_gp_event_select(idx, 0); + write_gp_counter_value(idx, 0); + } +} + +static inline void reset_all_fixed_counters(void) +{ + unsigned int idx; + + if (!pmu_nr_fixed_counters()) + return; + + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + for (idx = 0; idx < pmu_nr_fixed_counters(); idx++) + write_fixed_counter_value(idx, 0); +} + +static inline void reset_all_counters(void) +{ + reset_all_gp_counters(); + reset_all_fixed_counters(); +} + #endif /* _X86_PMU_H_ */ diff --git a/x86/pmu.c b/x86/pmu.c index 589c7cb..7786b49 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -397,7 +397,7 @@ static void check_rdpmc(void) .idx = i }; - wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, x); + write_fixed_counter_value(i, x); report(rdpmc(i | (1 << 30)) == x, "fixed cntr-%d", i); exc = test_for_exception(GP_VECTOR, do_rdpmc_fast, &cnt);