diff mbox series

[kvm-unit-tests,v4,22/24] x86/pmu: Add nr_gp_counters to limit the number of test counters

Message ID 20221024091223.42631-23-likexu@tencent.com (mailing list archive)
State New, archived
Headers show
Series x86/pmu: Test case optimization, fixes and additions | expand

Commit Message

Like Xu Oct. 24, 2022, 9:12 a.m. UTC 
From: Like Xu <likexu@tencent.com>

The number of counters in amd is fixed (4 or 6), and the test code
can be reused by dynamically switching the maximum number of counters
(and register base addresses), with no change for Intel side.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 lib/x86/pmu.c | 1 +
 lib/x86/pmu.h | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c
index 43e6a43..25e21e5 100644
--- a/lib/x86/pmu.c
+++ b/lib/x86/pmu.c
@@ -10,6 +10,7 @@  void pmu_init(void)
         pmu.perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);
     pmu.msr_gp_counter_base = MSR_IA32_PERFCTR0;
     pmu.msr_gp_event_select_base = MSR_P6_EVNTSEL0;
+    pmu.nr_gp_counters = (cpuid_10.a >> 8) & 0xff;
     if (this_cpu_support_perf_status()) {
         pmu.msr_global_status = MSR_CORE_PERF_GLOBAL_STATUS;
         pmu.msr_global_ctl = MSR_CORE_PERF_GLOBAL_CTRL;
diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h
index fa49a8f..4312b6e 100644
--- a/lib/x86/pmu.h
+++ b/lib/x86/pmu.h
@@ -54,6 +54,7 @@  struct pmu_caps {
     u32 msr_global_status;
     u32 msr_global_ctl;
     u32 msr_global_status_clr;
+    unsigned int nr_gp_counters;
 };
 
 extern struct cpuid cpuid_10;
@@ -123,7 +124,13 @@  static inline bool this_cpu_support_perf_status(void)
 
 static inline u8 pmu_nr_gp_counters(void)
 {
-	return (cpuid_10.a >> 8) & 0xff;
+	return pmu.nr_gp_counters;
+}
+
+static inline void set_nr_gp_counters(u8 new_num)
+{
+	if (new_num < pmu_nr_gp_counters())
+		pmu.nr_gp_counters = new_num;
 }
 
 static inline u8 pmu_gp_counter_width(void)