From patchwork Tue Oct 25 11:43:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudio Imbrenda X-Patchwork-Id: 13019105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1126C38A2D for ; Tue, 25 Oct 2022 11:44:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231315AbiJYLo2 (ORCPT ); Tue, 25 Oct 2022 07:44:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231909AbiJYLn6 (ORCPT ); Tue, 25 Oct 2022 07:43:58 -0400 Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A05A8175370 for ; Tue, 25 Oct 2022 04:43:56 -0700 (PDT) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29PB8Vp8011653 for ; Tue, 25 Oct 2022 11:43:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=DJ0rE5Sz18nIdU7QV1+Xe8vKpcL58TIlTo3KdsBO+S4=; b=HfO4f45/85GjdsIF1mn1NJUZDq2GG1SObTazv8NVvWB+v5VynEk90WBdFpYEisccIt3f t0ZuPX0J9I9rGAau1TxTmrFYA92pg9uis35ZF1m/lk3SYbwbMndVb9vhLshnJZ4Q/iNC Hz7aEMnCx9zk5NMEXRCFTFS/g9RAvGalJzClXQuVd1b4K5IU/y8P410GIYeAmC8rM00X fury9DLj+2vFpH/9YgUzfX0s1rGbcRP4ultVokZA2CaHOeABEplmTITbVaMmohs9BXDs WkbPrP1b4ee0fhZ/TLRULsfRkX321MjtHW2fxRhP5dG3o1XaxvOixwDXepQsXHvWr8j7 BA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3kee02tdp2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 25 Oct 2022 11:43:55 +0000 Received: from m0098420.ppops.net (m0098420.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 29PB9V1w015982 for ; Tue, 25 Oct 2022 11:43:55 GMT Received: from ppma01fra.de.ibm.com (46.49.7a9f.ip4.static.sl-reverse.com [159.122.73.70]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3kee02tdn9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Oct 2022 11:43:55 +0000 Received: from pps.filterd (ppma01fra.de.ibm.com [127.0.0.1]) by ppma01fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 29PBd65n011292; Tue, 25 Oct 2022 11:43:53 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma01fra.de.ibm.com with ESMTP id 3kc8593yv5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Oct 2022 11:43:53 +0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 29PBhp2I2228912 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 25 Oct 2022 11:43:51 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0766DAE045; Tue, 25 Oct 2022 11:43:51 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D0665AE04D; Tue, 25 Oct 2022 11:43:50 +0000 (GMT) Received: from p-imbrenda.boeblingen.de.ibm.com (unknown [9.152.224.252]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 25 Oct 2022 11:43:50 +0000 (GMT) From: Claudio Imbrenda To: pbonzini@redhat.com Cc: kvm@vger.kernel.org, thuth@redhat.com, frankja@linux.ibm.com Subject: [kvm-unit-tests GIT PULL 20/22] lib: s390x: Use a new asce for each PV guest Date: Tue, 25 Oct 2022 13:43:43 +0200 Message-Id: <20221025114345.28003-21-imbrenda@linux.ibm.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221025114345.28003-1-imbrenda@linux.ibm.com> References: <20221025114345.28003-1-imbrenda@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jND2ffGLAUkqAFsf4_fzngmMSILeSem0 X-Proofpoint-ORIG-GUID: omoQwgb1u0BJ120rHqTfso0gTDvU9prN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-25_05,2022-10-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210250067 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Janosch Frank Every PV guest needs its own ASCE so let's copy the topmost table designated by CR1 to create a new ASCE for the PV guest. Before and after SIE we now need to switch ASCEs to and from the PV guest / test ASCE. The SIE assembly function does that automatically. Signed-off-by: Janosch Frank Reviewed-by: Claudio Imbrenda Message-Id: <20221021063902.10878-5-frankja@linux.ibm.com> Signed-off-by: Claudio Imbrenda --- lib/s390x/sie.h | 2 ++ lib/s390x/uv.h | 5 ++--- lib/s390x/asm-offsets.c | 2 ++ lib/s390x/sie.c | 2 ++ lib/s390x/uv.c | 24 +++++++++++++++++++++++- s390x/cpu.S | 6 ++++++ 6 files changed, 37 insertions(+), 4 deletions(-) diff --git a/lib/s390x/sie.h b/lib/s390x/sie.h index 320c4218..3e3605c9 100644 --- a/lib/s390x/sie.h +++ b/lib/s390x/sie.h @@ -205,12 +205,14 @@ union { struct vm_uv { uint64_t vm_handle; uint64_t vcpu_handle; + uint64_t asce; void *conf_base_stor; void *conf_var_stor; void *cpu_stor; }; struct vm_save_regs { + uint64_t asce; uint64_t grs[16]; uint64_t fprs[16]; uint32_t fpc; diff --git a/lib/s390x/uv.h b/lib/s390x/uv.h index 44264861..5fe29bda 100644 --- a/lib/s390x/uv.h +++ b/lib/s390x/uv.h @@ -28,9 +28,8 @@ static inline void uv_setup_asces(void) /* We need to have a valid primary ASCE to run guests. */ setup_vm(); - /* Set P bit in ASCE as it is required for PV guests */ - asce = stctg(1) | ASCE_P; - lctlg(1, asce); + /* Grab the ASCE which setup_vm() just set up */ + asce = stctg(1); /* Copy ASCE into home space CR */ lctlg(13, asce); diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c index fbea3278..f612f327 100644 --- a/lib/s390x/asm-offsets.c +++ b/lib/s390x/asm-offsets.c @@ -75,9 +75,11 @@ int main(void) OFFSET(SIE_SAVEAREA_HOST_GRS, vm_save_area, host.grs[0]); OFFSET(SIE_SAVEAREA_HOST_FPRS, vm_save_area, host.fprs[0]); OFFSET(SIE_SAVEAREA_HOST_FPC, vm_save_area, host.fpc); + OFFSET(SIE_SAVEAREA_HOST_ASCE, vm_save_area, host.asce); OFFSET(SIE_SAVEAREA_GUEST_GRS, vm_save_area, guest.grs[0]); OFFSET(SIE_SAVEAREA_GUEST_FPRS, vm_save_area, guest.fprs[0]); OFFSET(SIE_SAVEAREA_GUEST_FPC, vm_save_area, guest.fpc); + OFFSET(SIE_SAVEAREA_GUEST_ASCE, vm_save_area, guest.asce); OFFSET(STACK_FRAME_INT_BACKCHAIN, stack_frame_int, back_chain); OFFSET(STACK_FRAME_INT_FPC, stack_frame_int, fpc); OFFSET(STACK_FRAME_INT_FPRS, stack_frame_int, fprs); diff --git a/lib/s390x/sie.c b/lib/s390x/sie.c index 3fee3def..6efad965 100644 --- a/lib/s390x/sie.c +++ b/lib/s390x/sie.c @@ -85,6 +85,8 @@ void sie_guest_create(struct vm *vm, uint64_t guest_mem, uint64_t guest_mem_len) /* Guest memory chunks are always 1MB */ assert(!(guest_mem_len & ~HPAGE_MASK)); + /* For non-PV guests we re-use the host's ASCE for ease of use */ + vm->save_area.guest.asce = stctg(1); /* Currently MSO/MSL is the easiest option */ vm->sblk->mso = (uint64_t)guest_mem; vm->sblk->msl = (uint64_t)guest_mem + ((guest_mem_len - 1) & HPAGE_MASK); diff --git a/lib/s390x/uv.c b/lib/s390x/uv.c index 3b4cafa9..b2a43424 100644 --- a/lib/s390x/uv.c +++ b/lib/s390x/uv.c @@ -90,6 +90,25 @@ void uv_init(void) initialized = true; } +/* + * Create a new ASCE for the UV config because they can't be shared + * for security reasons. We just simply copy the top most table into a + * fresh set of allocated pages and use those pages as the asce. + */ +static uint64_t create_asce(void) +{ + void *pgd_new, *pgd_old; + uint64_t asce = stctg(1); + + pgd_new = memalign_pages(PAGE_SIZE, PAGE_SIZE * 4); + pgd_old = (void *)(asce & PAGE_MASK); + + memcpy(pgd_new, pgd_old, PAGE_SIZE * 4); + + asce = __pa(pgd_new) | ASCE_P | (asce & (ASCE_DT | ASCE_TL)); + return asce; +} + void uv_create_guest(struct vm *vm) { struct uv_cb_cgc uvcb_cgc = { @@ -125,7 +144,8 @@ void uv_create_guest(struct vm *vm) vm->uv.cpu_stor = memalign_pages_flags(PAGE_SIZE, uvcb_qui.cpu_stor_len, 0); uvcb_csc.stor_origin = (uint64_t)vm->uv.cpu_stor; - uvcb_cgc.guest_asce = (uint64_t)stctg(1); + uvcb_cgc.guest_asce = create_asce(); + vm->save_area.guest.asce = uvcb_cgc.guest_asce; uvcb_cgc.guest_sca = (uint64_t)vm->sca; cc = uv_call(0, (uint64_t)&uvcb_cgc); @@ -166,6 +186,8 @@ void uv_destroy_guest(struct vm *vm) assert(cc == 0); free_pages(vm->uv.conf_base_stor); free_pages(vm->uv.conf_var_stor); + + free_pages((void *)(vm->uv.asce & PAGE_MASK)); } int uv_unpack(struct vm *vm, uint64_t addr, uint64_t len, uint64_t tweak) diff --git a/s390x/cpu.S b/s390x/cpu.S index 82b5e25d..45bd551a 100644 --- a/s390x/cpu.S +++ b/s390x/cpu.S @@ -76,6 +76,9 @@ sie64a: .endr stfpc SIE_SAVEAREA_HOST_FPC(%r3) + stctg %c1, %c1, SIE_SAVEAREA_HOST_ASCE(%r3) + lctlg %c1, %c1, SIE_SAVEAREA_GUEST_ASCE(%r3) + # Store scb and save_area pointer into stack frame stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area @@ -102,6 +105,9 @@ sie_exit: # Load guest register save area lg %r14,__SF_SIE_SAVEAREA(%r15) + # Restore the host asce + lctlg %c1, %c1, SIE_SAVEAREA_HOST_ASCE(%r14) + # Store guest's gprs, fprs and fpc stmg %r0,%r13,SIE_SAVEAREA_GUEST_GRS(%r14) # save guest gprs 0-13 .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15