| Message ID | 20221204174632.3677-12-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: improve boot time isa extensions handling | expand |
Reviewed-by: Guo Ren <guoren@kernel.org> On Mon, Dec 5, 2022 at 1:57 AM Jisheng Zhang <jszhang@kernel.org> wrote: > > Switch cpu_relax() from statich branch to the new helper > riscv_has_extension_likely() > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/riscv/include/asm/vdso/processor.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index fa70cfe507aa..edf0e25e43d1 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -10,7 +10,7 @@ > > static inline void cpu_relax(void) > { > - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { > #ifdef __riscv_muldiv > int dummy; > /* In lieu of a halt instruction, induce a long-latency stall. */ > -- > 2.37.2 >
On Mon, Dec 05, 2022 at 01:46:30AM +0800, Jisheng Zhang wrote: > Switch cpu_relax() from statich branch to the new helper The tiniest nit: static > riscv_has_extension_likely() > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > --- > arch/riscv/include/asm/vdso/processor.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index fa70cfe507aa..edf0e25e43d1 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -10,7 +10,7 @@ > > static inline void cpu_relax(void) > { > - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { > #ifdef __riscv_muldiv > int dummy; > /* In lieu of a halt instruction, induce a long-latency stall. */ > -- > 2.37.2 >
diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h index fa70cfe507aa..edf0e25e43d1 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -10,7 +10,7 @@ static inline void cpu_relax(void) { - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) { + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { #ifdef __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */