| Message ID | 20221209043804.942352-4-aik@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: SEV: Enable AMD SEV-ES DebugSwap | expand |
On Fri, Dec 09, 2022 at 03:38:04PM +1100, Alexey Kardashevskiy wrote: > With MSR_AMD64_SEV_DEBUG_SWAP enabled, the VM should not get #VC > events for DR7 read/write which it rather avoided. > > Signed-off-by: Alexey Kardashevskiy <aik@amd.com> > --- > Changes: > v2: > * use new bit definition > --- > arch/x86/include/asm/msr-index.h | 1 + > tools/arch/x86/include/asm/msr-index.h | 1 + > arch/x86/kernel/sev.c | 6 ++++++ > 3 files changed, 8 insertions(+) Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4a2af82553e4..979ea2dd3845 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index f17ade084720..2264ada2e26a 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a428c62330d3..6141c789e3d5 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1618,6 +1618,9 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, long val, *reg = vc_insn_get_rm(ctxt); enum es_result ret; + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED; @@ -1655,6 +1658,9 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, struct sev_es_runtime_data *data = this_cpu_read(runtime_data); long *reg = vc_insn_get_rm(ctxt); + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED;
With MSR_AMD64_SEV_DEBUG_SWAP enabled, the VM should not get #VC events for DR7 read/write which it rather avoided. Signed-off-by: Alexey Kardashevskiy <aik@amd.com> --- Changes: v2: * use new bit definition --- arch/x86/include/asm/msr-index.h | 1 + tools/arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/sev.c | 6 ++++++ 3 files changed, 8 insertions(+)