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[RFC,4/8] KVM: x86/pmu: Add Intel CPUID-hinted Topdown Slots event

Message ID 20221212125844.41157-5-likexu@tencent.com (mailing list archive)
State New, archived
Headers show
Series KVM: x86/pmu: Enable Fixed Counter3 and Topdown Perf Metrics | expand

Commit Message

Like Xu Dec. 12, 2022, 12:58 p.m. UTC 
From: Like Xu <likexu@tencent.com>

This event counts the total number of available slots for an unhalted
logical processor. Software can use this event as the denominator for the
top-level metrics of the Top-down Microarchitecture Analysis method.

Although the MSR_PERF_METRICS MSR required for topdown events is not
currently available in the guest, relying only on the data provided by
the slots event is sufficient for pmu users to perceive differences in
cpu pipeline machine-width across micro-architectures.

The standalone slots event, like the instruction event, can be counted
with gp counter or fixed counter 3 (if any). As the last CPUID-hinted
Architectural Performance Events, its availability is also controlled by
CPUID.AH.EBX. On the Linux, perf user may encode "-e cpu/event=0xa4,
umask=0x01/" or "-e cpu/slots/" to count slots events.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
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Patch

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index b746381307c7..d86a6ba8c3f9 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -31,10 +31,11 @@ 
  * 4 - PERF_COUNT_HW_CACHE_MISSES
  * 5 - PERF_COUNT_HW_BRANCH_INSTRUCTIONS
  * 6 - PERF_COUNT_HW_BRANCH_MISSES
+ * 7 - CPUID-hinted Topdown Slots event (available on gp counter)
  *
  * the second part of hw_events is defined by the generic kernel perf:
  *
- * 7 - PERF_COUNT_HW_REF_CPU_CYCLES
+ * 8 - PERF_COUNT_HW_REF_CPU_CYCLES
  */
 static struct kvm_pmu_hw_event intel_arch_events[] = {
 	[0] = { 0x3c, 0x00 },
@@ -44,12 +45,13 @@  static struct kvm_pmu_hw_event intel_arch_events[] = {
 	[4] = { 0x2e, 0x41 },
 	[5] = { 0xc4, 0x00 },
 	[6] = { 0xc5, 0x00 },
+	[7] = { 0xa4, 0x01 },
 	/* The above index must match CPUID 0x0A.EBX bit vector */
-	[7] = { 0x00, 0x03 },
+	[8] = { 0x00, 0x03 },
 };
 
 /* mapping between fixed pmc index and intel_arch_events array */
-static int fixed_pmc_events[] = {1, 0, 7};
+static int fixed_pmc_events[] = {1, 0, 8};
 
 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
 {
@@ -109,7 +111,7 @@  static bool intel_hw_event_available(struct kvm_pmc *pmc)
 			continue;
 
 		/* disable event that reported as not present by cpuid */
-		if ((i < 7) && !(pmu->available_event_types & (1 << i)))
+		if (i < 8 && !(pmu->available_event_types & (1 << i)))
 			return false;
 
 		break;