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Peter Anvin" Subject: [PATCH kernel v3 1/3] x86/amd: Cache debug register values in percpu variables Date: Fri, 20 Jan 2023 14:10:45 +1100 Message-ID: <20230120031047.628097-2-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230120031047.628097-1-aik@amd.com> References: <20230120031047.628097-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT058:EE_|CY5PR12MB6647:EE_ X-MS-Office365-Filtering-Correlation-Id: 3474bb54-6ed3-4278-fa2d-08dafa942804 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LL//HUOJZPb2A0n9zNw2roP4Ef6rwCHnFVRBdqf8wxie4GKBhoKkGRYfPP9FUardLGKN0uslrH9+dMmhpADGEDNwlS90NkIIpvT+B7MQiiucgdsK4H0jRap8D79d92ivVth4W9x+iyZeOC1KvpkgU7HCOZoWO5GKVCYZgEqe041eu9uoyIpzO/NdtCHfjcOWpzng6CFTWP/jTIGRGkJS+hnuVNS8M/tPX9sxzsCEg4mlcLqFOw1UG9J9belsI2KHDrIV4JVCR4SQmt7RRCGZzqHn97YGCjsb3WzPmKkVUPVQOrpraCxtAbTjR40rrJ0/zR+y0Gpf0UAwYrdlSx6JmuMVFqBjczZD0v/8HG2lUBRkLmUgS/Ixz22X8aa+l7It+nAlMzRgBhUxHxWnct7yX2qT8jKXd0ndetxyFzlku0IRUQhIVV1q0grn3dG41zVzvTjqK6quQLFj8bcdlV/98A4TshUxiPs+G/Lfqzcl/UhGMLH5wvbEu6iEH/VWOYJSPD5eJCeQxQUkD4zx+UIVNZIHIxxldvYj7/8d58CA7OKXrmkhhxD0yf6upsYCU1WhP3agVu/IjySmIgtHIPa5L5XqMLFdmK4aBcdSUWsR+OpSM15VIa/kflAIm4OeKK6XJJywsGsrlkfDe0pTYfYDODooQI9chwaKVGolVeRJUcInKc6JJVeP9C7enFiV5j4kR1huREKhAnQkuZtX8iriuPViKB9k3N/j48cSphPkNOU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(396003)(346002)(451199015)(46966006)(40470700004)(36840700001)(6666004)(70586007)(70206006)(4326008)(336012)(478600001)(1076003)(16526019)(26005)(8676002)(186003)(426003)(47076005)(41300700001)(83380400001)(5660300002)(6862004)(7416002)(8936002)(2906002)(36860700001)(6200100001)(81166007)(356005)(40480700001)(82740400003)(7049001)(2616005)(37006003)(316002)(54906003)(40460700003)(36756003)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 03:12:25.8771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3474bb54-6ed3-4278-fa2d-08dafa942804 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6647 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Reading DR[0-3]_ADDR_MASK MSRs takes about 250 cycles which is going to be noticeable with the AMD KVM SEV-ES DebugSwap feature enabled. KVM is going to store host's DR[0-3] and DR[0-3]_ADDR_MASK before switching to a guest; the hardware is going to swap these on VMRUN and VMEXIT. Store MSR values passed to set_dr_addr_mask() in percpu variables (when changed) and return them via new amd_get_dr_addr_mask(). The gain here is about 10x. As set_dr_addr_mask() uses the array too, change the @dr type to unsigned to avoid checking for <0. And give it the amd_ prefix to match the new helper as the whole DR_ADDR_MASK feature is AMD-specific anyway. While at it, replace deprecated boot_cpu_has() with cpu_feature_enabled() in set_dr_addr_mask(). Signed-off-by: Alexey Kardashevskiy --- Changes: v3: * fixed commit log * amd_msr_dr_addr_masks do not do "-1" * store processor id in a local variable * s/set_dr_addr_mask/amd_set_dr_addr_mask/ v2: * reworked to use arrays * set() skips wrmsr() when the mask is not changed * added stub for get_dr_addr_mask() * changed @dr type to unsigned * s/boot_cpu_has/cpu_feature_enabled/ * added amd_ prefix --- arch/x86/include/asm/debugreg.h | 9 +++- arch/x86/kernel/cpu/amd.c | 47 ++++++++++++++------ arch/x86/kernel/hw_breakpoint.c | 4 +- 3 files changed, 42 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h index b049d950612f..f126b2ee890f 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -126,9 +126,14 @@ static __always_inline void local_db_restore(unsigned long dr7) } #ifdef CONFIG_CPU_SUP_AMD -extern void set_dr_addr_mask(unsigned long mask, int dr); +extern void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr); +extern unsigned long amd_get_dr_addr_mask(unsigned int dr); #else -static inline void set_dr_addr_mask(unsigned long mask, int dr) { } +static inline void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) { } +static inline unsigned long amd_get_dr_addr_mask(unsigned int dr) +{ + return 0; +} #endif #endif /* _ASM_X86_DEBUGREG_H */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 208c2ce8598a..380753b14cab 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1158,24 +1158,43 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) return false; } -void set_dr_addr_mask(unsigned long mask, int dr) +static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); + +static unsigned int amd_msr_dr_addr_masks[] = { + MSR_F16H_DR0_ADDR_MASK, + MSR_F16H_DR1_ADDR_MASK, + MSR_F16H_DR1_ADDR_MASK + 1, + MSR_F16H_DR1_ADDR_MASK + 2 +}; + +void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) { - if (!boot_cpu_has(X86_FEATURE_BPEXT)) + int cpu = smp_processor_id(); + + if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) return; - switch (dr) { - case 0: - wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); - break; - case 1: - case 2: - case 3: - wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); - break; - default: - break; - } + if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) + return; + + if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) + return; + + wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); + per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; +} + +unsigned long amd_get_dr_addr_mask(unsigned int dr) +{ + if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) + return 0; + + if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) + return 0; + + return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); } +EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); u32 amd_get_highest_perf(void) { diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c index bbb0f737aab1..b01644c949b2 100644 --- a/arch/x86/kernel/hw_breakpoint.c +++ b/arch/x86/kernel/hw_breakpoint.c @@ -127,7 +127,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp) set_debugreg(*dr7, 7); if (info->mask) - set_dr_addr_mask(info->mask, i); + amd_set_dr_addr_mask(info->mask, i); return 0; } @@ -166,7 +166,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) set_debugreg(dr7, 7); if (info->mask) - set_dr_addr_mask(0, i); + amd_set_dr_addr_mask(0, i); /* * Ensure the write to cpu_dr7 is after we've set the DR7 register.