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Peter Anvin" Subject: [PATCH kernel v3 3/3] x86/sev: Do not handle #VC for DR7 read/write Date: Fri, 20 Jan 2023 14:10:47 +1100 Message-ID: <20230120031047.628097-4-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230120031047.628097-1-aik@amd.com> References: <20230120031047.628097-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT035:EE_|DM4PR12MB7622:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d553487-8014-4529-f8c2-08dafa944890 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R3JO53eyfBJpXDk7B8dWVFm02xOS6WpdG8jCcw9o+t7UZtdYNnTRQcqi/VusWuL4tpS8pG0BWsIvZeVIaHYo4ZI2k4CSSA8YOZJ3gUnFdyWvWCPTs7SC3UlVFMTw9TBhnWTPwLT1zcSZtarYyOozT9XsRd/lk077kAvK/BgBKE8hK6iarPQdc9TUjCqqzzB7nD6LIyBXk/Hl5p8VFnGdyHVjPMAfuxu8Wiy1hYUG4+4VZ+fgE2LG7U2o2hV2aOY0Ddsoh/KKwGxOMZ8lfoqLkIAx02HpJrnVwdFH0Dm7ComEoIplHCZdsRnhBQepFZYVrAnucbsQRRi6s6aHrU3o9HWOGgffAmUPP8BJcJ/4C45WzQDlu8c0ghiq2rwzRCo8ZU0hlUD9D8ploR54YXw0yzmmIdfBIeTCi+jekPpBh7DbND565jknAq0uMiYqmhml/FIDsn/GqRazrAU/VZOhe4o2bBPs6MQPolP5VcoBdM/IVLKs3Hptlvsr+O9UxmY1nNDItSlf7/3s7+7PF1QHOWct7rSwIbgcaqAy3gJZSMp8OI04VEk2xDLMX7LcRoAOSper30/naHknMFKZowsrFNaGZyMsqPzd7qNCEutsYlQHGfpD3HIg05wAhNh/wZ8JgNBTiDHxEMoUxQ8HEZDhTlFV9KVB719PrpCwPis6PTME8lzGg+NGcnyfSr9M7qP96bXh4zNSh7EV4xpVNLlJ68B6yNYGnUosMD1NXDJIa9s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(376002)(136003)(451199015)(40470700004)(36840700001)(46966006)(82740400003)(81166007)(36860700001)(7049001)(5660300002)(356005)(2906002)(8676002)(4326008)(7416002)(6862004)(8936002)(70586007)(70206006)(426003)(40480700001)(2616005)(6200100001)(82310400005)(478600001)(47076005)(16526019)(186003)(26005)(336012)(1076003)(316002)(54906003)(41300700001)(40460700003)(6666004)(37006003)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 03:13:20.5129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d553487-8014-4529-f8c2-08dafa944890 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7622 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org With MSR_AMD64_SEV_DEBUG_SWAP enabled, the VM should not get #VC events for DR7 read/write which it rather avoided. Signed-off-by: Alexey Kardashevskiy Reviewed-by: Borislav Petkov (AMD) --- Changes: v2: * use new bit definition --- arch/x86/include/asm/msr-index.h | 1 + tools/arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/sev.c | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index cb3d0f6e6ac2..e15afe3500ff 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -574,6 +574,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 37ff47552bcb..27c1c349e49b 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -565,6 +565,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 679026a640ef..8184f8ba4edc 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1618,6 +1618,9 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, long val, *reg = vc_insn_get_rm(ctxt); enum es_result ret; + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED; @@ -1655,6 +1658,9 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, struct sev_es_runtime_data *data = this_cpu_read(runtime_data); long *reg = vc_insn_get_rm(ctxt); + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED;