| Message ID | 20230126165351.2561582-7-ricarkol@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: pmu: Add support for PMUv3p5 | expand |
Hi Ricardo, On 1/26/23 17:53, Ricardo Koller wrote: > test_overflow_interrupt() (from arm/pmu.c) has a test that passes > because the previous test leaves the state needed to pass: the > overflow status register with the expected bits. The test (that should > fail) does not enable the PMU after mem_access_loop(), which clears > the PMCR, and before writing into the software increment register. > > Fix by clearing the previous test state (pmovsclr_el0) and by enabling > the PMU before the sw_incr test. > > Fixes: 4f5ef94f3aac ("arm: pmu: Test overflow interrupts") > Reported-by: Reiji Watanabe <reijiw@google.com> > Signed-off-by: Ricardo Koller <ricarkol@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Thank you for the fix! Eric > --- > arm/pmu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arm/pmu.c b/arm/pmu.c > index 1e93ea2..f91b5ca 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -914,10 +914,15 @@ static void test_overflow_interrupt(bool overflow_at_64bits) > > write_regn_el0(pmevcntr, 0, pre_overflow); > write_regn_el0(pmevcntr, 1, pre_overflow); > + write_sysreg(ALL_SET_32, pmovsclr_el0); > write_sysreg(ALL_SET_32, pmintenset_el1); > isb(); > > mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); > + > + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); > + isb(); > + > for (i = 0; i < 100; i++) > write_sysreg(0x3, pmswinc_el0); >
diff --git a/arm/pmu.c b/arm/pmu.c index 1e93ea2..f91b5ca 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -914,10 +914,15 @@ static void test_overflow_interrupt(bool overflow_at_64bits) write_regn_el0(pmevcntr, 0, pre_overflow); write_regn_el0(pmevcntr, 1, pre_overflow); + write_sysreg(ALL_SET_32, pmovsclr_el0); write_sysreg(ALL_SET_32, pmintenset_el1); isb(); mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); + + set_pmcr(pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp); + isb(); + for (i = 0; i < 100; i++) write_sysreg(0x3, pmswinc_el0);
test_overflow_interrupt() (from arm/pmu.c) has a test that passes because the previous test leaves the state needed to pass: the overflow status register with the expected bits. The test (that should fail) does not enable the PMU after mem_access_loop(), which clears the PMCR, and before writing into the software increment register. Fix by clearing the previous test state (pmovsclr_el0) and by enabling the PMU before the sw_incr test. Fixes: 4f5ef94f3aac ("arm: pmu: Test overflow interrupts") Reported-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Ricardo Koller <ricarkol@google.com> --- arm/pmu.c | 5 +++++ 1 file changed, 5 insertions(+)