[25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
        kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
        palmer@dabbelt.com, alistair.francis@wdc.com,
        bin.meng@windriver.com, pbonzini@redhat.com,
        philipp.tomsich@vrull.eu, kvm@vger.kernel.org
Subject: [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding,
 translation and execution support
Date: Thu,  2 Feb 2023 12:42:16 +0000
Message-Id: <20230202124230.295997-26-lawrence.hunter@codethink.co.uk>
In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk>
References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk>
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Message ID	20230202124230.295997-26-lawrence.hunter@codethink.co.uk (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Date: Thu, 2 Feb 2023 12:42:16 +0000 Message-Id: <20230202124230.295997-26-lawrence.hunter@codethink.co.uk> In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add RISC-V vector cryptography extensions \| expand [00/39] Add RISC-V vector cryptography extensions [01/39] target/riscv: add zvkb cpu property [02/39] target/riscv: Add vclmul.vv decoding, translation and execution support [03/39] target/riscv: Add vclmul.vx decoding, translation and execution support [04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support [05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support [06/39] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution supp… [07/39] target/riscv: Add vbrev8.v decoding, translation and execution support [08/39] target/riscv: Add vrev8.v decoding, translation and execution support [09/39] target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution support [10/39] target/riscv: expose zvkb cpu property [11/39] target/riscv: add zvkns cpu property [12/39] target/riscv: Add vaesef.vv decoding, translation and execution support [13/39] target/riscv: Add vaesef.vs decoding, translation and execution support [14/39] target/riscv: Add vaesdf.vv decoding, translation and execution support [15/39] target/riscv: Add vaesdf.vs decoding, translation and execution support [16/39] target/riscv: Add vaesdm.vv decoding, translation and execution support [17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support [18/39] target/riscv: Add vaesz.vs decoding, translation and execution support [19/39] target/riscv: Add vaesem.vv decoding, translation and execution support [20/39] target/riscv: Add vaesem.vs decoding, translation and execution support [21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support [22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support [23/39] target/riscv: expose zvkns cpu property [24/39] target/riscv: add zvknh cpu properties [25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support [26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support [27/39] target/riscv: expose zvknh cpu properties [28/39] target/riscv: add zvksh cpu property [29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support [30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support [31/39] target/riscv: expose zvksh cpu property [32/39] target/riscv: add zvkg cpu property [33/39] target/riscv: Add vghmac.vv decoding, translation and execution support [34/39] target/riscv: expose zvkg cpu property [35/39] crypto: Move SM4_SBOXWORD from target/riscv [36/39] crypto: Add SM4 constant parameter CK. [37/39] target/riscv: Add zvksed cfg property [38/39] target/riscv: Add Zvksed support [39/39] target/riscv: Expose Zvksed property

[25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support

Commit Message

Patch