From patchwork Thu Feb 2 12:42:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lawrence Hunter X-Patchwork-Id: 13125996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25DAEC636D4 for ; Thu, 2 Feb 2023 13:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232090AbjBBNTf (ORCPT ); Thu, 2 Feb 2023 08:19:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232084AbjBBNTe (ORCPT ); Thu, 2 Feb 2023 08:19:34 -0500 Received: from imap5.colo.codethink.co.uk (imap5.colo.codethink.co.uk [78.40.148.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72E58497D for ; Thu, 2 Feb 2023 05:19:31 -0800 (PST) Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pNYvL-004Q6t-2O; Thu, 02 Feb 2023 12:42:43 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 31/39] target/riscv: expose zvksh cpu property Date: Thu, 2 Feb 2023 12:42:22 +0000 Message-Id: <20230202124230.295997-32-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> References: <20230202124230.295997-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a412d9d53..a3b08e9d27 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1097,6 +1097,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), + DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false), /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),