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Mon, 6 Feb 2023 06:06:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT016.mail.protection.outlook.com (10.13.173.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6064.34 via Frontend Transport; Mon, 6 Feb 2023 06:06:18 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 6 Feb 2023 00:05:55 -0600 From: Manali Shukla To: CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH kernel 1/2] perf/x86/amd: Add amd_prevent_hostibs_window() to set per-cpu ibs_flags Date: Mon, 6 Feb 2023 06:05:44 +0000 Message-ID: <20230206060545.628502-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230206060545.628502-1-manali.shukla@amd.com> References: <20230206060545.628502-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT016:EE_|IA0PR12MB8205:EE_ X-MS-Office365-Filtering-Correlation-Id: 2593ba35-0b5e-424f-6589-08db08084358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2023 06:06:18.4903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2593ba35-0b5e-424f-6589-08db08084358 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8205 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a function to set per-cpu ibs_flags based on an active or inactive PreventHostIBS window. MSR_AMD64_IBSFETCHCTL[IbsFetchEn] and MSR_AMD64_IBSOPCTL[IbsOpEn] bits need to be cleared for PreventHostIBS feature to be enabled before VMRUN is executed. ENABLE bit and VALID bit for MSR_AMD64_IBSFETCHCTL are contained in the same MSR and same is the case with MSR_AMD64_IBSOPCTL. Consider the following scenario: - The IBS MSR which has ENABLE bit set and VALID bit clear is read. - During the process of clearing the ENABLE bit and writing the IBS MSR to disable IBS, an IBS event can occur that sets the VALID bit. - The write operation on IBS MSR can clear the newly set VALID bit. - Since this situation is occurring in the CLGI/STGI window (PreventHostIBS window), the actual NMI is not taken. - Once VMRUN is issued, it will exit with VMEXIT_NMI. As soon as STGI is executed, the pending NMI will trigger. - The IBS NMI handler checks for the VALID bit to determine if the NMI is generated because of IBS. - Since VALID bit is now clear, it doesn't recognize that an IBS event is occurred. Due to this reason, the dazed and confused unknown NMI messages are generated. amd_prevent_hostibs_window() is added to avoid these messages when PreventHostIBS window is active and PreventHostIBS feature is enabled for the guest. Signed-off-by: Manali Shukla Reviewed-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 64 +++++++++++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 20 ++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index da3f5ebac4e1..e96a4c9ff4ba 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -30,7 +30,9 @@ static u32 ibs_caps; #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT +#define PREVENT_HOSTIBS_WINDOW BIT(0) +static DEFINE_PER_CPU(unsigned int, ibs_flags); /* * IBS states: @@ -1035,6 +1037,18 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) if (test_and_clear_bit(IBS_STOPPED, pcpu->state)) return 1; + /* + * Catch NMIs generated in an active PreventHostIBS window: + * incoming NMIs from an active PreventHostIBS window might have + * the VALID bit cleared when it is supposed to be set due to + * a race. The reason for the race is ENABLE and VALID bits for + * MSR_AMD64_IBSFETCHCTL and MSR_AMD64_IBSOPCTL being in their + * same respective MSRs. Ignore all such NMIs and treat them as + * handled. + */ + if (__this_cpu_read(ibs_flags) & PREVENT_HOSTIBS_WINDOW) + return 1; + return 0; } @@ -1540,3 +1554,53 @@ static __init int amd_ibs_init(void) /* Since we need the pci subsystem to init ibs we can't do this earlier: */ device_initcall(amd_ibs_init); + +void amd_prevent_hostibs_window(bool active) +{ + if (active) + __this_cpu_write(ibs_flags, + __this_cpu_read(ibs_flags) | + PREVENT_HOSTIBS_WINDOW); + else + __this_cpu_write(ibs_flags, + __this_cpu_read(ibs_flags) & + ~PREVENT_HOSTIBS_WINDOW); +} +EXPORT_SYMBOL_GPL(amd_prevent_hostibs_window); + +bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl) +{ + *ibs_fetch_ctl = __rdmsr(MSR_AMD64_IBSFETCHCTL); + if (!(*ibs_fetch_ctl & IBS_FETCH_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, + *ibs_fetch_ctl & ~IBS_FETCH_ENABLE); + + return true; +} +EXPORT_SYMBOL(amd_disable_ibs_fetch); + +bool amd_disable_ibs_op(u64 *ibs_op_ctl) +{ + *ibs_op_ctl = __rdmsr(MSR_AMD64_IBSOPCTL); + if (!(*ibs_op_ctl & IBS_OP_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSOPCTL, *ibs_op_ctl & ~IBS_OP_ENABLE); + + return true; +} +EXPORT_SYMBOL(amd_disable_ibs_op); + +void amd_restore_ibs_fetch(u64 ibs_fetch_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, ibs_fetch_ctl); +} +EXPORT_SYMBOL(amd_restore_ibs_fetch); + +void amd_restore_ibs_op(u64 ibs_op_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSOPCTL, ibs_op_ctl); +} +EXPORT_SYMBOL(amd_restore_ibs_op); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 5d0f6891ae61..1005505e23b1 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -561,6 +561,26 @@ static inline void intel_pt_handle_vmx(int on) } #endif +#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_CPU_SUP_AMD) +extern void amd_prevent_hostibs_window(bool active); +extern bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl); +extern bool amd_disable_ibs_op(u64 *ibs_op_ctl); +extern void amd_restore_ibs_fetch(u64 ibs_fetch_ctl); +extern void amd_restore_ibs_op(u64 ibs_op_ctl); +#else +static inline void amd_prevent_hostibs_window(bool active) {} +static inline bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl) +{ + return false; +} +static inline bool amd_disable_ibs_op(u64 *ibs_op_ctl) +{ + return false; +} +static inline void amd_restore_ibs_fetch(u64 ibs_fetch_ctl) {} +static inline void amd_restore_ibs_op(u64 ibs_op_ctl) {} +#endif + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) extern void amd_pmu_enable_virt(void); extern void amd_pmu_disable_virt(void);