diff mbox series

[RESEND,kvm-unit-tests,3/3] arm64: microbench: Use gic_enable_irq() macro in microbench test

Message ID 20230302030238.158796-4-shahuang@redhat.com (mailing list archive)
State New, archived
Headers show
Series arm: Use gic_enable/disable_irq() macro to clean up code | expand

Commit Message

Shaoqin Huang March 2, 2023, 3:02 a.m. UTC
Use gic_enable_irq() to clean up code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
---
 arm/micro-bench.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

Comments

Eric Auger March 2, 2023, 8:19 a.m. UTC | #1
Hi Shaoqin,

On 3/2/23 04:02, Shaoqin Huang wrote:
> Use gic_enable_irq() to clean up code.
> 
> Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  arm/micro-bench.c | 15 +--------------
>  1 file changed, 1 insertion(+), 14 deletions(-)
> 
> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
> index 8436612..090fda6 100644
> --- a/arm/micro-bench.c
> +++ b/arm/micro-bench.c
> @@ -212,24 +212,11 @@ static void lpi_exec(void)
>  
>  static bool timer_prep(void)
>  {
> -	void *gic_isenabler;
> -
>  	gic_enable_defaults();
>  	install_irq_handler(EL1H_IRQ, gic_irq_handler);
>  	local_irq_enable();
>  
> -	switch (gic_version()) {
> -	case 2:
> -		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
> -		break;
> -	case 3:
> -		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
> -		break;
> -	default:
> -		assert_msg(0, "Unreachable");
> -	}
> -
> -	writel(1 << PPI(TIMER_VTIMER_IRQ), gic_isenabler);
> +	gic_enable_irq(PPI(TIMER_VTIMER_IRQ));
>  	write_sysreg(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
>  	isb();
>
diff mbox series

Patch

diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 8436612..090fda6 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -212,24 +212,11 @@  static void lpi_exec(void)
 
 static bool timer_prep(void)
 {
-	void *gic_isenabler;
-
 	gic_enable_defaults();
 	install_irq_handler(EL1H_IRQ, gic_irq_handler);
 	local_irq_enable();
 
-	switch (gic_version()) {
-	case 2:
-		gic_isenabler = gicv2_dist_base() + GICD_ISENABLER;
-		break;
-	case 3:
-		gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
-		break;
-	default:
-		assert_msg(0, "Unreachable");
-	}
-
-	writel(1 << PPI(TIMER_VTIMER_IRQ), gic_isenabler);
+	gic_enable_irq(PPI(TIMER_VTIMER_IRQ));
 	write_sysreg(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
 	isb();