| Message ID | 20230303031148.162816-2-shahuang@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: Use gic_enable/disable_irq() macro to clean up code | expand |
diff --git a/lib/arm/gic.c b/lib/arm/gic.c index 1bfcfcf..89a15fe 100644 --- a/lib/arm/gic.c +++ b/lib/arm/gic.c @@ -176,7 +176,6 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest) void gic_irq_set_clr_enable(int irq, bool enable) { u32 offset, split = 32, shift = (irq % 32); - u32 reg, mask = BIT(shift); void *base; assert(irq < 1020); @@ -199,8 +198,7 @@ void gic_irq_set_clr_enable(int irq, bool enable) assert(0); } base += offset + (irq / split) * 4; - reg = readl(base); - writel(reg | mask, base); + writel(BIT(shift), base); } enum gic_irq_state gic_irq_state(int irq)
When use gic_irq_set_clr_enable() to disable an interrupt, it will disable all interrupt since it first read from Interrupt Clear-Enable Registers where '1' indicates that forwarding of the corresponding interrupt is enabled and then write this value with a mask into Interrupt Clear-Enable Registers where '1' indicates disable the forwarding of the corresponding interrupt. So directly write one bit per time to enable or disable interrupt. Fixes: cb573c2 ("arm: gic: Introduce gic_irq_set_clr_enable() helper") Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> --- lib/arm/gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)