[01/45] target/riscv: Add zvkb cpu property

Message ID	20230310091215.931644-2-lawrence.hunter@codethink.co.uk (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 01/45] target/riscv: Add zvkb cpu property Date: Fri, 10 Mar 2023 09:11:31 +0000 Message-Id: <20230310091215.931644-2-lawrence.hunter@codethink.co.uk> In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> References: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add RISC-V vector cryptographic instruction set support \| expand [00/45] Add RISC-V vector cryptographic instruction set support [01/45] target/riscv: Add zvkb cpu property [02/45] target/riscv: Refactor some of the generic vector functionality [03/45] target/riscv: Add vclmul.vv decoding, translation and execution support [04/45] target/riscv: Refactor some of the generic vector functionality [05/45] target/riscv: Add vclmul.vx decoding, translation and execution support [06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support [07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support [08/45] target/riscv: Refactor some of the generic vector functionality [09/45] qemu/bitops.h: Limit rotate amounts [10/45] target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution supp… [11/45] target/riscv: Refactor some of the generic vector functionality [12/45] target/riscv: Add vbrev8.v decoding, translation and execution support [13/45] target/riscv: Add vrev8.v decoding, translation and execution support [14/45] target/riscv: Add vandn.[vv,vx] decoding, translation and execution support [15/45] target/riscv: Expose zvkb cpu property [16/45] target/riscv: Add zvkned cpu property [17/45] target/riscv: Add vaesef.vv decoding, translation and execution support [18/45] target/riscv: Add vaesef.vs decoding, translation and execution support [19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support [20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support [21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support [22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support [23/45] target/riscv: Add vaesz.vs decoding, translation and execution support [24/45] target/riscv: Add vaesem.vv decoding, translation and execution support [25/45] target/riscv: Add vaesem.vs decoding, translation and execution support [26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support [27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support [28/45] target/riscv: Expose zvkned cpu property [29/45] target/riscv: Add zvknh cpu properties [30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support [31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support [32/45] target/riscv: Expose zvknh cpu properties [33/45] target/riscv: Add zvksh cpu property [34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support [35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support [36/45] target/riscv: Expose zvksh cpu property [37/45] target/riscv: Add zvkg cpu property [38/45] target/riscv: Add vgmul.vv decoding, translation and execution support [39/45] target/riscv: Add vghsh.vv decoding, translation and execution support [40/45] target/riscv: Expose zvkg cpu property [41/45] crypto: Create sm4_subword [42/45] crypto: Add SM4 constant parameter CK [43/45] target/riscv: Add zvksed cfg property [44/45] target/riscv: Add Zvksed support [45/45] target/riscv: Expose Zvksed property

Message ID

20230310091215.931644-2-lawrence.hunter@codethink.co.uk (mailing list archive)

State

New, archived

Headers

From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
        kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
        palmer@dabbelt.com, alistair.francis@wdc.com,
        bin.meng@windriver.com, pbonzini@redhat.com,
        philipp.tomsich@vrull.eu, kvm@vger.kernel.org
Subject: [PATCH 01/45] target/riscv: Add zvkb cpu property
Date: Fri, 10 Mar 2023 09:11:31 +0000
Message-Id: <20230310091215.931644-2-lawrence.hunter@codethink.co.uk>
In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk>
References: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Add RISC-V vector cryptographic instruction set support | expand

Commit Message

Lawrence Hunter March 10, 2023, 9:11 a.m. UTC

From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
 target/riscv/cpu.c | 13 +++++++++++++
 target/riscv/cpu.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..69611408f9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -109,6 +109,7 @@  static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
     ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
+    ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb),
     ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1211,6 +1212,18 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+    * In principle zve*x would also suffice here, were they supported
+    * in qemu
+    */
+    if (cpu->cfg.ext_zvkb &&
+        !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f ||
+            cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) {
+        error_setg(
+            errp, "Vector crypto extensions require V or Zve* extensions");
+        return;
+    }
+
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.pmu_num) {
         if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..7d6699f718 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -470,6 +470,7 @@  struct RISCVCPUConfig {
     bool ext_zve32f;
     bool ext_zve64f;
     bool ext_zve64d;
+    bool ext_zvkb;
     bool ext_zmmul;
     bool ext_zvfh;
     bool ext_zvfhmin;

[01/45] target/riscv: Add zvkb cpu property

Commit Message

Patch