From patchwork Fri Mar 17 11:35:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13178955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75F6CC76195 for ; Fri, 17 Mar 2023 11:37:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230274AbjCQLha (ORCPT ); Fri, 17 Mar 2023 07:37:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230265AbjCQLhO (ORCPT ); Fri, 17 Mar 2023 07:37:14 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FFCCE1912 for ; Fri, 17 Mar 2023 04:36:49 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id d13so4811746pjh.0 for ; Fri, 17 Mar 2023 04:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1679053006; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=q2CeCkoiCmH3/ws0KZkp+HQfm92M4kXVwNFV93ZjvNY=; b=B4MOa9IepBe7fu/GGyQMpi02t840NVUsF1YMHv1IHWQgDBAY8KAE0VLig75obbBRAN D97f7SkMS7O887HHAA9b4Roq1/r79WMLcP9T7gh7HJZsnpRtJRvsQk9UvRXcGc58yKao tF0KteeSLzOAngaNz/1+UR0VzpVA/A8qbNC1/NU+NDPz3eShXQ9A2lI3Aiw4Sb5pt33V 4aGUeGm80Mb6VR5j1+lkO0MFTB/+N3/T6sRpl80mzcb4Y3B+vLbgm1LzEj3952Ge7FmN nIluRiTK6Qe2SZevotJVVFwSUQzOvvqA6UfL68RDPdyX8al/OlTgBP7fPPyIHMhvWUWi JXlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679053006; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q2CeCkoiCmH3/ws0KZkp+HQfm92M4kXVwNFV93ZjvNY=; b=DmbIpPVU/rf8pOgfCRfP3zIOofPaVkxco47fwf12LiVL/rRv9APxnWmiX3ysDm4HQy L3/4cLIaTUaix5pzbSpHOuK/WJatKIjR7lhQbL3CiBvwqqkWXImVYITuSXo4wuKZ7aBT MXVKrYlKct/ZF0W+3mahNGhjzf7MHVlDAqbArUed6mYzm033/lL4u+AAzZ9d/Ouh1Ah3 n0yqsfNmC8dLekQAiNupTjXxz7S5yX1bgMiPaxbo8Z+7dAmRSKFSBLEaoX0Jujj4GIvz cVYAgC48p4NQM3W9cWHYcIr6V2/EuKJn3DT4kEgS/ebiQa30Y3YWxCaRMq2+i2ZQ1ZFA khqw== X-Gm-Message-State: AO0yUKV7v0WuECYiEpqkt3pTLSDPSS6KKLbY+Ac8GhxFj/57xfl9kzfj OCEhzSLOVI6/dzrpplamEsNpLQ== X-Google-Smtp-Source: AK7set/jJt9RpQRdgFNr/nwnCHvluLee730CaOiZ9z5NnZShDPmF2cgAcce7IEv3RBA0ymK3/kp/eQ== X-Received: by 2002:a17:90b:3a87:b0:23f:ef7:7897 with SMTP id om7-20020a17090b3a8700b0023f0ef77897mr7686906pjb.49.1679053005719; Fri, 17 Mar 2023 04:36:45 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id n63-20020a17090a2cc500b0023d3845b02bsm1188740pjd.45.2023.03.17.04.36.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 04:36:45 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Han-Kuan Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Nicolas Saenz Julienne , Frederic Weisbecker , Andrew Bresticker , Jisheng Zhang , Conor Dooley , Alexandre Ghiti , Masahiro Yamada Subject: [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself Date: Fri, 17 Mar 2023 11:35:24 +0000 Message-Id: <20230317113538.10878-6-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com> References: <20230317113538.10878-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren Disable vector instructions execution for kernel mode at its entrances. Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Han-Kuan Chen Signed-off-by: Han-Kuan Chen Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 99d38fdf8b18..e38676d9a0d6 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -77,10 +77,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3fd6a4bd9c3e..e16bb2185d55 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -140,10 +140,10 @@ secondary_start_sbi: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 /* Set trap vector to spin forever to help debug */ @@ -234,10 +234,10 @@ pmp_done: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 #ifdef CONFIG_RISCV_BOOT_SPINWAIT