[-next,v17,20/20] riscv: Enable Vector code to be built

Commit Message

Andy Chiu March 27, 2023, 4:49 p.m. UTC

From: Guo Ren <[e-mail]>

This patch adds a config which enables vector feature from the kernel
space.

Signed-off-by: Guo Ren <[e-mail]>
Co-developed-by: Greentime Hu <[e-mail]>
Signed-off-by: Greentime Hu <[e-mail]>
Suggested-by: Vineet Gupta <[e-mail]>
Suggested-by: Atish Patra <[e-mail]>
Co-developed-by: Andy Chiu <[e-mail]>
Signed-off-by: Andy Chiu <[e-mail]>
Reviewed-by: Conor Dooley <[e-mail]>
---
 arch/riscv/Kconfig  | 20 ++++++++++++++++++++
 arch/riscv/Makefile |  6 +++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

Comments

Heiko Stuebner March 31, 2023, 1:32 p.m. UTC | #1

Am Montag, 27. März 2023, 18:49:40 CEST schrieb Andy Chiu:
> From: Guo Ren <[e-mail]>
> 
> This patch adds a config which enables vector feature from the kernel
> space.
> 
> Signed-off-by: Guo Ren <[e-mail]>
> Co-developed-by: Greentime Hu <[e-mail]>
> Signed-off-by: Greentime Hu <[e-mail]>
> Suggested-by: Vineet Gupta <[e-mail]>
> Suggested-by: Atish Patra <[e-mail]>
> Co-developed-by: Andy Chiu <[e-mail]>
> Signed-off-by: Andy Chiu <[e-mail]>
> Reviewed-by: Conor Dooley <[e-mail]>

Reviewed-by: Heiko Stuebner <[e-mail]>
Tested-by: Heiko Stuebner <[e-mail]>

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 91d5f2731f06..d95245311bf0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -443,6 +443,26 @@  config RISCV_ISA_SVPBMT
 
 	   If you don't know what to do here, say Y.
 
+config TOOLCHAIN_HAS_V
+	bool
+	default y
+	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
+	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
+	depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
+	depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_V
+	bool "VECTOR extension support"
+	depends on TOOLCHAIN_HAS_V
+	depends on FPU
+	select DYNAMIC_SIGFRAME
+	default y
+	help
+	  Say N here if you want to disable all vector related procedure
+	  in the kernel.
+
+	  If you don't know what to do here, say Y.
+
 config TOOLCHAIN_HAS_ZBB
 	bool
 	default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6203c3378922..6f32c0ab32e3 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -56,6 +56,7 @@  riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
 riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
 riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+riscv-march-$(CONFIG_RISCV_ISA_V)	:= $(riscv-march-y)v
 
 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.
@@ -65,7 +66,10 @@  riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
 # Check if the toolchain supports Zihintpause extension
 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
 
-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
+# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
+KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
+
 KBUILD_AFLAGS += -march=$(riscv-march-y)
 
 KBUILD_CFLAGS += -mno-save-restore