diff mbox series

[RFC,2/7] x86/entry: Add IST main stack

Message ID 20230403140605.540512-3-jiangshanlai@gmail.com (mailing list archive)
State New, archived
Headers show
Series x86/entry: Atomic statck switching for IST | expand

Commit Message

Lai Jiangshan April 3, 2023, 2:06 p.m. UTC 
From: Lai Jiangshan <jiangshan.ljs@antgroup.com>

Add IST main stack for atomic-IST-entry.

The size is THREAD_SIZE since there might be multiple super
exceptions being handled on the stack.

Signed-off-by: Lai Jiangshan <jiangshan.ljs@antgroup.com>
---
 Documentation/x86/kernel-stacks.rst   | 2 ++
 arch/x86/include/asm/cpu_entry_area.h | 5 +++++
 arch/x86/kernel/dumpstack_64.c        | 6 ++++--
 arch/x86/mm/cpu_entry_area.c          | 1 +
 4 files changed, 12 insertions(+), 2 deletions(-)

Comments

Linus Torvalds April 3, 2023, 4:21 p.m. UTC | #1 
On Mon, Apr 3, 2023 at 7:05 AM Lai Jiangshan <jiangshanlai@gmail.com> wrote:
>
> diff --git a/Documentation/x86/kernel-stacks.rst b/Documentation/x86/kernel-stacks.rst
> index 6b0bcf027ff1..be89acf302da 100644
> --- a/Documentation/x86/kernel-stacks.rst
> +++ b/Documentation/x86/kernel-stacks.rst
> @@ -105,6 +105,8 @@ The currently assigned IST stacks are:
>    middle of switching stacks.  Using IST for MCE events avoids making
>    assumptions about the previous state of the kernel stack.
>
> +* ESTACK_IST. bla bla
> +
>  For more details see the Intel IA32 or AMD AMD64 architecture manuals.

Maybe the cover letter description could be used here, rather than the
"bla bla" placeholder?

              Linus
Peter Zijlstra April 6, 2023, 8:51 p.m. UTC | #2 
On Mon, Apr 03, 2023 at 10:06:00PM +0800, Lai Jiangshan wrote:
> diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
> index f05339fee778..3413b23fa9f1 100644
> --- a/arch/x86/kernel/dumpstack_64.c
> +++ b/arch/x86/kernel/dumpstack_64.c
> @@ -26,11 +26,12 @@ static const char * const exception_stack_names[] = {
>  		[ ESTACK_MCE	]	= "#MC",
>  		[ ESTACK_VC	]	= "#VC",
>  		[ ESTACK_VC2	]	= "#VC2",
> +		[ ESTACK_IST	]	= "#IST",
>  };

Since #IST is not actually a vector, perhaps ditch the '#' ?
diff mbox series

Patch

diff --git a/Documentation/x86/kernel-stacks.rst b/Documentation/x86/kernel-stacks.rst
index 6b0bcf027ff1..be89acf302da 100644
--- a/Documentation/x86/kernel-stacks.rst
+++ b/Documentation/x86/kernel-stacks.rst
@@ -105,6 +105,8 @@  The currently assigned IST stacks are:
   middle of switching stacks.  Using IST for MCE events avoids making
   assumptions about the previous state of the kernel stack.
 
+* ESTACK_IST. bla bla
+
 For more details see the Intel IA32 or AMD AMD64 architecture manuals.
 
 
diff --git a/arch/x86/include/asm/cpu_entry_area.h b/arch/x86/include/asm/cpu_entry_area.h
index 462fc34f1317..a373e8c37e25 100644
--- a/arch/x86/include/asm/cpu_entry_area.h
+++ b/arch/x86/include/asm/cpu_entry_area.h
@@ -10,6 +10,8 @@ 
 
 #ifdef CONFIG_X86_64
 
+#define IST_MAIN_STKSZ	THREAD_SIZE
+
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 #define VC_EXCEPTION_STKSZ	EXCEPTION_STKSZ
 #else
@@ -30,6 +32,8 @@ 
 	char	VC_stack[optional_stack_size];			\
 	char	VC2_stack_guard[guardsize];			\
 	char	VC2_stack[optional_stack_size];			\
+	char	IST_stack_guard[guardsize];			\
+	char	IST_stack[IST_MAIN_STKSZ];			\
 	char	IST_top_guard[guardsize];			\
 
 /* The exception stacks' physical storage. No guard pages required */
@@ -52,6 +56,7 @@  enum exception_stack_ordering {
 	ESTACK_MCE,
 	ESTACK_VC,
 	ESTACK_VC2,
+	ESTACK_IST,
 	N_EXCEPTION_STACKS
 };
 
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index f05339fee778..3413b23fa9f1 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -26,11 +26,12 @@  static const char * const exception_stack_names[] = {
 		[ ESTACK_MCE	]	= "#MC",
 		[ ESTACK_VC	]	= "#VC",
 		[ ESTACK_VC2	]	= "#VC2",
+		[ ESTACK_IST	]	= "#IST",
 };
 
 const char *stack_type_name(enum stack_type type)
 {
-	BUILD_BUG_ON(N_EXCEPTION_STACKS != 6);
+	BUILD_BUG_ON(N_EXCEPTION_STACKS != ARRAY_SIZE(exception_stack_names));
 
 	if (type == STACK_TYPE_TASK)
 		return "TASK";
@@ -89,6 +90,7 @@  struct estack_pages estack_pages[CEA_ESTACK_PAGES] ____cacheline_aligned = {
 	EPAGERANGE(MCE),
 	EPAGERANGE(VC),
 	EPAGERANGE(VC2),
+	EPAGERANGE(IST),
 };
 
 static __always_inline bool in_exception_stack(unsigned long *stack, struct stack_info *info)
@@ -98,7 +100,7 @@  static __always_inline bool in_exception_stack(unsigned long *stack, struct stac
 	struct pt_regs *regs;
 	unsigned int k;
 
-	BUILD_BUG_ON(N_EXCEPTION_STACKS != 6);
+	BUILD_BUG_ON(N_EXCEPTION_STACKS != 7);
 
 	begin = (unsigned long)__this_cpu_read(cea_exception_stacks);
 	/*
diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c
index 7316a8224259..62341cb819ab 100644
--- a/arch/x86/mm/cpu_entry_area.c
+++ b/arch/x86/mm/cpu_entry_area.c
@@ -148,6 +148,7 @@  static void __init percpu_setup_exception_stacks(unsigned int cpu)
 	cea_map_stack(NMI);
 	cea_map_stack(DB);
 	cea_map_stack(MCE);
+	cea_map_stack(IST);
 
 	if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
 		if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {